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Flashcards in Scribe Acronyms Deck (45):
1

NCHLVSA

n-channel - low-voltage - sense-amp

2

PCHLVSA

p-channel - low-voltage - sense-amp

3

NCHLVIO

n-channel - low-voltage - i/o

4

NCHEQA

n-channel - equilizer A?

5

VDL

Valid Device List

6

BEOL

Back End Of Line 

(metal layers)

7

MSR

Minimum Structure Requirement 

8

AMD

Advance Mask Developement (group)

9

FP

(First Partial etch)

The first of two dry etch steps required to complete a pattern.

10

FCVD

(flowable chemical vapor Deposition)

A CVD oxide depositon process where the oxide flows after deposition to round corners and fill voids.

11

FRESCO

(Fluorine Resist Etch Stop Coat)

Plasma-based carbon-doped silicon nitride that is resistan to HF.

12

FEB

(Full Etchback)

The process of removing all of the dielectric films used to form the conainers in the periphery.

13

HARP

(High Aspect Ratio Process)

A CVD oxide deposition process that produces a high-denisty oxide in narrow trences.

14

ISSG

(insitu Steam generation)

A method of thermal oxidation in a single-wafer chamber that produces a high-quality oxide with minimal silicon consumption.

15

LP

(Last Partial etch)

The second of two dry etch steps requried to complete a pattern.

16

Lattice

A layer of silicon nitride that provides stability for DRAM capacitors.

17

MLR

(Multi Layer Resist)

A low-cost hardmask scheme that utilizes two spin-on films: Underlayer and Hardmask.

18

NBTI

(Negative biased temp. instability)

PMOS interface state generation and/or hole trapping in the gate oxide for PMOS devices in inversion.

19

NTD

(Negative Tone Develop)

A photot process where uniqe developer chemestry removes the unexposed resist. It is used to imporve resolution of small contacts or trenches.

20

21

PWL

(passing worldline)

in 3x2 architecture, PWL is the portion of the wordline that passes between active areas.

22

Pixer

A reticle correction technique utilizing the addition of individual pixels to improve reticle field CDU (critical dimention uniformity)

23

Rails

A method of forming of cell contacts through the formation of rails of nitride (or other films) and then depositing the cell contact material between the rails.

24

RDL

(redistribution Layer)

A tungsten contact that corrects for misalignment between the cell contacts and capacitors.

25

RELACS

A photo process that reduces the printed CD by depositing a second layer on the inside surface of the openings in the resist.

26

RPD

( Reverse pitch doubling)

A method of pitch doubling that yields matched pairs of trenches.

27

RH

(Row Hammer)

Tests run during the burn-in (also probe) where a set of row is repeatedly pulsed with a hight voltage to determine the amount of degradation on the adjacent rows.

28

STI

(shallow Trench Isolation)

Oxide-filled trenches that electrically isolate adjacent active areas.

29

SPN

(Spa Plasma Nitridizaion)

Creates a SiON protective layer preventing dopant diffusion through the gate oxide. Process has a nitride plasma implant followed by a thermal anneal.

30

SOD

(spin-on Dielectric)

An oxide deposition process in which a liquid film is spun on the wafer and then densified into a solid oxide film.

31

TCAD

(Technology computer Aided design)

The use of coomputer simulation tools to predict the physical and electrical results of semiconductor process.

32

Wordline Disturb

Degraditon in the performance of DRAM cell due to activation of adjacent wordlines.

33

34

ALD

(Atomic layer Deposition)

Extermely conformal deposition of very thin films.

35

BCD (Poly)

(Balanced Controlled Deposition)

 

New recipe for polysilicon deposition that has fewer voids and better interface with single crystal silicon.

36

BLOK

(Barrier Lo-K)

Silicon-Carbon-Nitride film used as an etch stop and protective layer for backend metal.

37

BPSG

(Boro-Phospho-silicate Glass)

Low-density dielectric film, doped with boron and phosphorous, used for filling gaps in topography. Usually deposited very thick.

38

BARC

(Bottom AntiReflective Coating)

Spin-on film applied under photoresist. BARC minimizes substrate reflectivity and planarizes the surface to improve photo pattern integrity.

39

CC

(Cell Contact)

The conductive path from the access device to the capacitor in a DRAM cell. Also known as: Cellcon.

40

CHC

(channel Hot Carrier)

CMOS transistor aging caused by channel impact-ionization during saturated conduction at high drain voltage.

41

DARC

(Dielectric Anti-reflecting Coating)

A CVD SiON film that minimizes susbtrate reflectivity to improve photo pattern integrity.

42

DLC

(Diamond Like Carbon)

Very erosion-resistant and toppling-resistant carbon hardmask film.

43

DC

(Digit contact)

The conductive path from the access device to the digitline in a DRAM cell. Also known as: Bit Contact, Bitcon, Digitcon

44

DPD

(Double Pitch Doubling)

Mehthod of patterning regular arrays of very small contacts (or Capacitors)

45

Dual Damascene

The process of fomring copper interconects where copper is deposited in trenches, and the surface copper is removed using CMP.