Shift Registers and CMOS logic gates Flashcards Preview

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Flashcards in Shift Registers and CMOS logic gates Deck (18):
1

Describe an OR gate in terms of:

Boolean algebra

Circuit diagram

Truth table

 

2

Describe an XOR gate in terms of:

Boolean algebra

Circuit diagram

Truth table

 

3

Describe an NAND gate in terms of:

Boolean algebra

Circuit diagram

Truth table

 

4

Describe how to create a SIPO (Serial in, parallel out) shift register

A series of connected D flip-flops

5

Show how to make a 2 to 1 multiplexer with AND, NOT and or gates

6

Show how to make a 2-1 multiplexer with just NAND gates

7

Show how to make a 2-1 multiplexer using transmission gates and inverters

8

How do you create a PISO (Parallel In Serial Out) shift register using multiplexers and D flip-flops?

What does it do on Load/Shift hi and lo?

IF Load/Shift hi the D flip-flops are loaded with B0-3 on active clock edge.

IF Load/Shift lo then the data shifts right on clock edge

9

Describe the purpose of a parity bit in Shift register applications

It is added for error detection when transmitting data. It is set so the message signal has either even or odd number of 1's in it. This is then checked at the receiver which helps detect corruption.

10

What does CMOS stand for?

Complementary Metal Oxide Semiconductor technology

11

Show how to create a NOT gate using CMOS technology (NMOS/PMOS)

12

For an input square wave draw the output voltage and current drawn from a CMOS inverter

13

Draw a NAND gate using CMOS

14

Draw a NOR gate using CMOS

15

Draw an AND gate using CMOS and explain why it is not commonly used

We cannot implement AND with simple pull-up and pull-down networks so must invert our NAND gate using 2 extra transistors which takes up more space and power and is undesirable.

16

What is the difference between PMOS and NMOS in terms of drive strength?

PMOS have less drive strength than NMOS

17

Why are NAND gates preferred to NOR?

NAND gates have PMOS in series and NMOS in parallel

NOR gates have NMOS in series and PMOS in parallel

Thus NAND gates are faster

They also occupy less area typically

18

What form do we want the boolean expression in to create a general CMOS gate without inversion?

How do we then create the pull-down/pull-up networks?

We want F=not(SOP)

The pull down network is then SOP

The pull up is the Product of not(Sums) given by deMorgan