1.1.1

Question 1

Arithmetic Logic Unit ( ALU )

Answer 1

Carries out calculations and logical decisions

Question 2

Control Unit ( CU )

Answer 2

Manages operations within the CPU such as decoding instructions and controlling buses

Question 3

Registers

Answer 3

Small memory cells that operate at very high speeds and are used to temporarily store data

Question 4

Program Counter ( PC )

Answer 4

Holds the address of the next instruction to be executed and is incremented with each cycle of the FDE cycle

Question 5

Accumulator ( ACC )

Answer 5

Stores the results of calculations made by the ALU

Question 6

Memory Address Register ( MAR )

Answer 6

Stores the address of the next instruction or data to be read from or written to

Question 7

Memory Data Register ( MDR )

Answer 7

Temporarily stores data that has been read or needs to be written

Question 8

Current Instruction Register ( CIR )

Answer 8

Holds the current instruction being executed and is seperated into operand and opcode

Question 9

Buses

Answer 9

Set of parallel wires which connect components in the CPU together

Question 10

Bus Width

Answer 10

Number of parallel wires the bus has

Question 11

Data Bus

Answer 11

Transmit data between areas of the processors

Question 12

Address Bus

Answer 12

Used to carry the address to which the data is being transmitted

Question 13

Control Bus

Answer 13

Used to send control signals from the control unit to other parts of the processor

Question 14

Fetch

Answer 14

Address from PC is copied to the MAR
⬇️
Instruction in MAR is copied to the MDR
⬇️
Value held in MDR is copied to CIR

Question 15

Decode

Answer 15

Contents of CIR are sent to the CU
⬇️
CU then decodes the instruction

Question 16

Execute

Answer 16

The processor carries out the instruction

Question 17

Clock Speed

Answer 17

Clock speed means cycles per second
⬇️
The higher the clock speed , the less time a program will take to load

Question 18

Cache Memory

Answer 18

Cache memory is the CPU’s onboard memory
⬇️
Instructions fetched from main memory are copied to the cache , so if required again they can be accessed quicker

Question 19

Multiple Cores

Answer 19

Each core is an independent processor able to carry out its own FDE cycle
⬇️
Allowing the ability to multitask

Question 20

Pipelining

Answer 20

The process of completing FDE cycle of three separate instructions simultaneously
⬇️
Reduces the amount of the CPU that is kept idle

Question 21

Von Neumann Architecture

Answer 21

Uses a single control unit

Stores data and instructions in the same memory

Question 22

Harvard Architecture

Answer 22

Data and instructions are stored in separate memory units with separate buses

Question 23

Fetch-Decode-Execute Cycle

Answer 23

The sequence of operations that are completed in order to execute an instruction