Photolitography (intro, up to page 36)

Question 1

Absorption coefficient

Answer 1

The fractional decrease in the intensity of light
traveling through a material per unit distance traveled. Also called
Extinction Coefficient.

Question 2

Adhesion promoter

Answer 2

A chemical that is applied to the surface of a wafer in
order to improve the adhesion of resist to the wafer, often by eliminating
water from the wafer surface.

Question 3

Aerial image

Answer 3

An image of a mask pattern that is projected onto the

photoresist-coated wafer by an optical system.

Question 4

Antireflective coating (ARC)

Answer 4

A coating that is placed on top (TARC, Top
Antireflective Coating) or below (BARC, Bottom Antireflective Coating) the
layer of resist to reduce the reflection of light, and hence, reduce the
detrimental effects of standing waves or thin-film interference.

Question 5

Aspect ratio

Answer 5

The ratio of a feature’s height to its width.

Question 6

Bake

Answer 6

Thermal annealing of the photoresist

Question 7

Binary mask/ binary internsity mask

Answer 7

A mask made up of absorbing and transparent regions (for,example, one composed of chrome and glass) such that the transmittance of the mask is either 0 or 1.

Question 8

Chemically amplified resist/CAR

Answer 8

A type of photoresist, most commonly
used for deep-UV processes, which, upon post-exposure bake, will multiply the number of chemical reactions through the use of chemical catalysis.

Question 9

Catadioptric

Answer 9

An optical system made up of both refractive elements

lenses) and reflective elements (mirrors

Question 10

Catoptric

Answer 10

An optical system made up of only reflective elements

mirrors

Question 11

Critical dimension (CD)/Linewidth/feature width

Answer 11

The size (width) of a feature printed in resist, measured at a specific height above the substrate. (Over time, the meaning of “critical” has become vague, and it seems that any dimension worth measuring must be critical.)

Question 12

Spatial coherence

Answer 12

The phase relationship of light at two different points in space at any instant in time. For mask illumination, the spatial coherence is determined by the range of angles incident on the mask.

Question 13

Coherence illumination/Spatially coherent illumination

Answer 13

A type of illumination resulting from a point source of lightm that illuminates the mask with light from only one direction. This is more correctly
called spatially coherent illumination.

Question 14

Condenser lens

Answer 14

Lens system in an optical projection system that prepares light to illuminate the mask.

Question 15

Contrast enhancement layyer/material (CEL/CEM)

Answer 15

A highly bleachable coating on top of the photoresist that serves to enhance the contrast of an aerial image
projected through it. CEL results in improved resist sidewall angle, but at the cost of
reduced throughput. Condenser or
Mask or Proj

Question 16

Corner rounding

Answer 16

The rounding of a nominally sharp, square corner of a printed lithographic feature due to the inherent resolution limits of the patterning process.

Question 17

Cost of ownership

Answer 17

Cost estimate designed to help managers assessing the total cost of an investment, including the acquisition, the installation, the running cost and potentially the decommissioning. The running cost includes all the operational cost, including consumables, preventive and corrective maintenance, non-productive overhead,etc.

Question 18

Deep ultraviolet(DUV)/deep-UV

Answer 18

A common though vague term used to describe light of a wavelength in the range of about 150 nm to 300 nm. Also called deep-UV.

Question 19

Depth of focus (DOF)

Answer 19

The total range of focus that can be tolerated, i.e., the range of focus that keeps the resulting printed feature within a variety of specifications (such as linewidth, sidewall angle, resist loss, and exposure latitude).

Question 20

Design rule

Answer 20

A geometrical rule that defines minimum widths and/or spacings used when laying out a mask pattern.

Question 21

Design rule checker (DRC)

Answer 21

A software package that checks a chip design for compliance with a set of design rules.

Question 22

Diffraction

Answer 22

The propagation of light in the presence of boundaries. It is this property of light that causes the wavefront to bend as it passes an edge.

Question 23

Diffraction pattern

Answer 23

The pattern of light entering the objective lens due to diffraction by a mask.

Question 24

Dioptric

Answer 24

An optical system made up of only refractive elements (lenses).

Question 25

Dose-to-clear/clearing dose

Answer 25

The amount of exposure energy required to just clear the resist in a large clear area for a given process. Also called the clearing dose.

Question 26

Exposure energy/exposure dose/dose

Answer 26

The amount of energy (per unit area) that the photoresist is subjected to
upon exposure by a lithographic exposure system. For optical lithography it is equal to the
light intensity times the exposure time. Also called the exposure dose, or simply dose.

Question 27

Exposure field

Answer 27

The area of a wafer that is exposed at one time by the exposure tool.

Question 28

Exposure latitude

Answer 28

The range of exposure energies (usually expressed as a percent variation from the nominal) that keeps the linewidth within specified limits.

Question 29

Extreme Ultraviolet (EUV)/Soft x-ray

Answer 29

A common though vague term used to describe light of a wavelength in the range of about 5 nm to 50 nm. Also called soft x-ray.

Question 30

Focal plane

Answer 30

The plane of best focus of the optical system.

Question 31

Half pitch

Answer 31

Estimate of the maximum pattern density on a circuit for a given technology. The
actual value of the most aggressive half-pitch is no more a single target value for the whole
microelectronic industry, but depends on product type.

Question 32

HDMS

Answer 32

HexaMethylDiSilazane: Priming Material to improve Resist adhesion

Question 33

Illumination system

Answer 33

The light source and optical system designed to illuminate the mask for the purpose of forming an image on the wafer.

Question 34

Local CD uniformity (LCDU)

Answer 34

It is a measure of CD variability.

Question 35

Line edge roughness(LER)

Answer 35

The deviation of a feature edge (as viewed top down) from a smooth, ideal shape. That is, the edge deviations of a feature that occur on a dimensional
scale much smaller than the resolution limit of the imaging tool that was used to print the feature.

Question 36

Line end shortening (LES)/ Pull-back

Answer 36

The reduction of the length of a line (where a line is
defined here as any rectangular feature whose length is significantly greater than its width)
as measured only at one end. Thus, the line end shortening is characterized as the difference
between the actual position of the end of a line and the intended (designed) position.

Question 37

LWR

Answer 37

Line width roughess

Question 38

Manhattan design

Answer 38

Most of patterns (esp. interconnects) in an integrated circuit are laid out along the x and y directions: the so-called Manhattan design or architecture refers to this feature which takes the analogy with the way streets are organized in Manhattan’s borough
of New York City.

Question 39

Node

Answer 39

In the earlier International Technology Roadmaps for
Semiconductor, technology generations were described as technology nodes expressed as a
dimensional measure (e.g. 45 nm node). From 2005 owing to the different critical
dimensions related to different products (e.g. logic, DRAM or flash) this concept was
replaced by a definition of the half pitch.

Question 40

Normalized Image Log-Slope

Answer 40

The slope of the logarithm of an aerial image, measured at the desired photoresist edge position, normalized by multiplying by the nominal resist
feature width. Generally, the sign of the slope is adjusted to be positive.

Question 41

Numerical aperture(NA)

Answer 41

The sine of the maximum half-angle of light that can make it through a lens, multiplied by the index of refraction of the media.

Question 42

Objective lens/projection lens/imaging lens/reduction lens

Answer 42

The main imaging lens of a projection imaging system. Also called the projection lens, the imaging lens, or the reduction lens.

Question 43

Optical proximity correction (OPC)

Answer 43

Optical Proximity Correction (OPC): A method of selectively changing the sizes and shapes of
patterns on the mask in order to more exactly obtain the desired printed patterns on the wafer.

Question 44

Overlay/registration/alignment precision

Answer 44

A vector describing the positional accuracy with which a new lithographic pattern has been printed on top of an existing pattern on the wafer, measured at any point on the wafer. Also
called registration or alignment precision. Usually ~¼ of resolution.

Question 45

Patterning

Answer 45

Patterning: The processes of lithography (producing a pattern that covers portions of the
substrate with resist) followed by etching (selective removal of material not covered by resist) or
otherwise transferring the lithographic pattern into the substrate.

Question 46

Phase-shift-mask(PSM)

Answer 46

A mask that contains a designed spatial variation not only in intensity transmittance but phase transmittance as well.

Question 47

Photoactive compound (PAC)

Answer 47

The component of a photoresist that is sensitive to light.

Question 48

Photoresist contrast

Answer 48

A measure of the resolving power of a photoresist, the photoresist contrast is defined as the slope of the log-development rate versus log-exposure energy curve as the thickness of resist approaches zero. The photoresist contrast is usually given the symbol γ.

Question 49

Pitch

Answer 49

The sum of the linewidth and spacewidth for a repeating pattern of long lines and spaces. Pattern Period (Line + Space). If CD line = CD space then CD = ½ Pitch

Question 50

Process latitude

Answer 50

The range over which a process parameter can be varied such that the lithographic results are still acceptable.

Question 51

Reflective notching

Answer 51

An unwanted notching or local feature size change in a photoresist pattern caused by the reflection of light off nearby topographic patterns on the wafer.

Question 52

Resolution

Answer 52

The smallest feature of a given type that can be printed with acceptable quality and
control. For example, resolution is often defined as the smallest feature of a given type that meets
a given depth of focus requirement.

Question 53

Resolution enhancement technique (RET)

Answer 53

A collection of techniques such as optical proximity correction, phase-shift masks, and off-axis illumination, designed to improve the usable resolution of an optical lithography tool of a given numerical aperture and wavelength.

Question 54

Reticle

Answer 54

Lithographic mask employed in projection lithography.

Question 55

Serif

Answer 55

A small ancillary pattern attached to the corners of the original pattern on a mask in order to improve the printing fidelity of the pattern (see OPC).

Question 56

Sidewall angle

Answer 56

The angle that a resist profile makes with the substrate, usually estimated by modeling the resist profiles as a trapezoid.

Question 57

Standing waves

Answer 57

A periodic variation of intensity as a function of depth into the resist that results from interference between a plane wave of light traveling down through the photoresist and one that is reflected up from the substrate.

Question 58

Sub-resolution Assist feature (SRAF)

Answer 58

Small features, usually in the form of parallel lines, that
are below the resolution limit of the imaging system but influence the lithographic behavior of the larger feature they are near. A common form of such sub-resolution assist features are often called scattering bars.

Question 59

Typical photolithography process flow

Answer 59

1 Priming
2 Resist coating 
3 Resist softbake
4 Resist exposure
5 Resist post exposure bake
6 Resist image developing
7 Resist hard bake

Question 60

Different ages of scaling

Answer 60

1 Geometrical scaling (1975-2002)
Reduction of horizontal and vertical physical dimensions in conjunction with improved performance of planar transistors;
2 Equivalent scaling (2003-2024)
Redcution of only horizontal dimensions in conjunction with introduction of new materials and new physical effects. New vertical structures replace the planar transistor.
3 3D power scaling (2025-2040)
Transition to complete vertical device structures. Heterogeneous integration in conjunction with reduced power consumption become the technology drivers.

Question 61

Change in the definition of technology node

Answer 61

1960s-late 1990s: referred to the transistor’s gate length (Lg) which was also considered the “minimum feature size“ (Critical Dimension, CD).

From 1992: dimension of the smallest pitch typically utilized by the densest metal layer to be found in any integrated circuit (since in the 70s, 80s and the most of the 90s the dimensions of the gate length and of the half-pitch of the tightest metal lines were essentially the same; therefore this value was chosen as the node name since it conveyed with a single number the concept of density and performance).

By 2006: as microprocessors started dominating the technology scaling, ITRS replaced the term with a number of separate indicators for Flash, DRAM, and MPU/ASIC.

More recently: due to various marketing and discrepancies among foundries, the number itself has lost the exact meaning it once held.

Finally: the technology node definition became 70% of whatever the name of the node of the previous generation was !

Question 62

Why do semiconductor companies concentrated on the transistor design effort on refucing power consumption instead of maximizing transistor speed?

Answer 62

Reduction of gate length dimension by itself has no longer a dominant influence on the performance of
logic circuits. This is due to the severe power limitations that emerged in the middle of the previous decade. In order to limit power values to the 120-130 W range (i.e., no wafer cooling needed) it was no longer possible to increase operational frequency beyond the 5-6 GHz and therefore faster transistors no longer translated into to a higher operating frequency.
For this reason, semiconductor companies concentrated the transistor design effort on reducing power consumption instead of maximizing transistor speed since IC power dissipation has become a major design constraint. However, reduction in
contacted gate pitch is essential to increasing transistor density.
(!!!) In a few words, transistors are still getting faster generation-to-generation but not at the same rate than what used to be achieved in the 90s, since the major emphasis in transistor design has now shifted from speed to limiting power consumption.

Question 63

More than Moore (what is it?)

Answer 63

In the last decade a second trend appeared, characterized by functional diversification of semiconductor-based devices.
These non-digital functionalities do contribute to the miniaturization of electronic systems, although they do not necessarily scale at the same rate as the one that describes the development of digital functionality. Consequently, in view of added
functionality, this trend was designated “More-than-Moore” (MtM).
This includes the interaction with the outside world through an appropriate transduction (sensors and actuators) and the subsystem for powering the product.
These functions may imply analog and mixed signal processing, the incorporation of passive components, high-voltage components, MEMS, sensors and actuators, and micro-fluidic devices enabling biological functionalities.

Question 64

Virtuous cycles of Moore and More than Moore

Answer 64

MOORE:
Transistor scaling –> Better perfromance/cost–>Market growth–>Investment–>transistor scaling…
MORE THAN MOORE
Technology,device and circuit innovations, system integration –> Increased functionality, and/or lower cost–> market growth–> investment

Question 65

Why over the last 20 years most companies would drop out of More Moore scaling?

Answer 65

3 factors must be considered:
-Skyrocketing costs of new fabs
-High volume, high utilization: To amortize such a huge investment within a few years, a fab needs high
utilization rates
-Increasing complexity and R&D intensiveness

Question 66

What requirements does a lithographic processhave to fulfill?

Answer 66

-Capability of printing the smallest patterns (resolution, linewidth, critical dimension) as predicted by the Moore’s law;
-Small variations in dimensions (linewidth control) over large wafers, over different equipments and
fabrication lots, over time, …
-Large Depth of Focus (tolerance of non-planar substrates and thick resists)
-Precise alignment (overlay, registration) of all layers constitutive of the circuit (up to 80- 100);
-Capacity of obtaining repeatable patterns with a well defined 3D shape (CD variation < 10%);
-Defect Control: no additional pattern (dust, bubbles, …) must be imaged;
-Economical Efficiency: capability of controlling the fabrication costs as a function of the market targeted by the product (reduce the cost per function in integrated circuits):
• Low cost for masks, resists, exposure tools, sources, maintenance, …
• High Throughput
• High Yield (reliability)

Question 67

Litography yield

Answer 67

Global processing yield is dependent on every step’s yield
Lithographic steps are then critical in terms of cost,
performance, but also yield.
Typical fabrication facilities (fabs) have product yields > 95% so the lithography yield per step must be > 99%.
To achieve such a yield, huge investments on tools, process development (resists)
and control (in line and off line metrology) have been provided since 6 decades.
The litographic cost is around 30% of the whole manufacturing cost!

Question 68

IDM, Foundry and fabless models

Answer 68

Merchant or pure play foundries: only manufacture devices for other companies, without designing them.
A semiconductor company that designs, manufactures and sells integrated circuits (ICs) is an integrated device manufacturer (IDM). Basically they ship their designs to a semiconductor foundry for manufacturing.

Why?
In a mature semiconductor industry where the product complexity is high, integrated circuit production facilities are expensive to build and
maintain, it is impractical and cost prohibitive for one company to handle all the processes. Unless they can be kept at nearly full utilization, large facilities become a drain on the finances of the company that owns them. One consequence is that today the number of IDM has drastically reduced.