4 Flashcards

1
Q

V_il is threshold voltage for n transistor

A
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2
Q

V_ih is threshold voltage of pmos

A

Noise margins

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3
Q

Propagation delay is with respect to

A

Output. T_phl

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4
Q

Propagation average

A

T_phl + T_plh /2

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5
Q

Rise and Fall time for input can be different from

A

Rise and fall times in output.

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6
Q

An nmos inverter (not cmos) consists of

A

A pull up resistor with a nmos as pull down

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7
Q

Pmos inverter consists of

A

Pmos as pull up and resistor as pull down

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8
Q

The larger the resistor

A

The larger the area on chip than transistors.

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9
Q

Diode mode configuration of mosfet

A

Drain and gate of mosfet get shorted to get it to be like a diode or a resistor.

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10
Q

How can resistance be adjusted in a mosfet

A

Reduce W and L or size of transistor.

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11
Q

CMOS has drawback

A

Larger area on chip than nmos circuits but cmos allows us to control rise and fall time.

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12
Q

Drawback of nmos circuits

A

Large power consumption because there is resistance now. P = v^2 / R

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13
Q

In CMOS there is no current (i=0)

A

So static power of CMOS is 0!! But in reality there is a slight resistance in fets (in picoAmpere range) that cannot be avoided.

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14
Q

Static power =

A

P_s = VDD ×Idd

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15
Q

Dynamic power loss =

A

P_d = C×(Vdd^2) ×f

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16
Q

Transient voltage

A

Voltage range of which power supply oscillates

17
Q

Dynamic power loss cannot be avoided

A

Only reduced

18
Q

Voltage has a bigger role in power consumption and we can always reduce voltage

A

Voltage scaling is used. We can reduce voltage although we cannot reduce too much since we need a threshold voltage.

19
Q

With C_l large, slow rise and fall time

A

With C_l small, fast rise and fall time.

20
Q

Increasing width in on condition, R is reduced and faster rise and fall time.

A
21
Q

Lump capacitor

A

Combines multiple capacitors into one capacitor. In Power consumption, c represents internal capacitors as well as C_l.

22
Q

Crowbar current

A

V shape current. In transition state it turns on every time the switch from 0 to 1 happens. Or leakage current. Faster rise and fall times lead to less area under current and less power.

23
Q

Pullup network takes circuit to logic 1

A
24
Q

Pull down network takes to logic 0

A
25
Q

There is a tradeoff between static power and dynamic power consumption.

A

Decreasing static increases dynamic power.

26
Q

Lithography

A

Process using light exposure in which we create a pattern on a silicon wafer (remove silicon dioxide insulation layer)