S5-P1 Flashcards
New concepts
1
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Important Note: You must choose a number that’s present in all the options’ sequences, because we many never enter that number in the sequence. Here we choose 7.
Note On T FlipFlops: A T flip-flop is a type of digital circuit that has a single input and a single output. The input is called the toggle input (T), and the output changes state (toggles) when the toggle input is high and the clock signal is applied. If the toggle input is low, the T flip-flop holds the previous state. The T flip-flop is also known as a toggle flip-flop because it can toggle its output depending on the input.
What does it mean the counter is preset in the question? When a T flip-flop is preset, it means that the output of the flip-flop is set to a known state, regardless of the clock signal or any other synchronous inputs. The preset input is an asynchronous input that sets the output of the flip-flop to a high state when activated. So this means that at the begining, C,B,A are all 1. that’s why all the options start with 7.
4
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Note: We should write the states of each cycle and count, this number gives us the MOD-n.
Important Note On Ring Counter: To initialize it, we must put 10000, it DOES NOT initialize with zero. unless the question determines another bit as 1, we assume the MSB is 1.
Johnson Counter CAN initialize with 0.
F is 0 by default at first.
Ring Counter shifts to right by each clock.
The second FlipFlop’s clock is E, so the circuit is asynchronous, and when E goes from 0 to 1, the clock pulse is released AND since J and K are 1, Whatever’s at F, is complemented.
We must continue the shifts till we start repeating (the sequence of ABCDEF)
Note On JK FlipFlops: A JK flip-flop is a type of digital circuit that is used in sequential logic circuits for storing binary information in a bitwise manner. The JK flip-flop has two inputs, J and K, and two outputs, Q and Q’.
The JK flip-flop works as follows:
When J=0 and K=0, the output Q remains in its previous state.
When J=0 and K=1, the output Q is reset to 0.
When J=1 and K=0, the output Q is set to 1.
When J=1 and K=1, the output Q toggles between 0 and 1.
* new concept
4
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A state diagram for a synchronous circuit is a graphical representation of the states and transitions of a sequential circuit
Note On The Diagram: the notations on the arrows are input/output.
Note On Option 1: based on 1, 0010010 should give output 1, and it does .BUT for 00100010 which is a sequence of 0010, it doesn’t give us the output 1. so this model doesn’t give 1 for every sequence of 0010.
Note On Option 3: In Mealy Models, the number of states are equal to the number of the bits of the seq. it’s designed to distinguish. In Moore it’s one more.
What does it mean when it says overlapping sequences are allowed??? Why 1 is wrong??? The overlap part is correct, it’s the every seq. at the first part that’s not correct.
new concept
3
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Note: The last bit of an n bit number, is the remainder of it, when divided by 2. so if it’s 0, the number is even.
Note: When we shift an n bit number to the left, the LSB is 0, and all the other bits move to their left bits, so it’s as if we have multiplied that number by two. Here we have put B1=0, so it’s like we have multiplied every number by 2, the max of B4B3B2B1 would be 14, which is 7 x 2, so B4B3B2 must be connected to A1A2A3, this way, when the counter is 1, the output is 2 (doubled) so it can go up to 7, which its double is 14, ~A4 (because it’s active low) must connect to CLEAR so we start counting evens from 0. and LOAD must be 0 so we start from 0 when the counter begins to work.
Note On Load Terminal: The load terminal in a synchronous binary counter is a control input that allows the counter to be loaded with a preset value. The load terminal is typically labeled as “LD” or “LOAD” and is used to initialize the counter to a specific value when the circuit is powered on or reset. When the load terminal is activated, the counter is loaded with the preset value, and the counting operation begins from that value.
new concept
4
Note: A Circuit where the input affects on the output is Mealy and the input is for the user to put it so it’s asynchronous. But Moore is synchronous and the output changes with the clock pulse.
new concept
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Note: In Mealy, the output is written on the edges (links), In Moore the output is written on the states. because in Moore, the output doesn’t depend on input but in Mealy, it does.
Note: Mealy and Moore are DFAs so 4 can’t be the answer because for state “a” and “b” we have no outward 0 link. “c” is not definit because goest to 2 different states with 0.
Note On Sequence Detection: By default a sequence detector, must detect overlap too. option 4 detects 1101101 (an overlapping seq.) meaning that it’ll return 1 for this overlapping sequence.
Seq. detector w/ overlap using Mealy Model
Seq. detector W/ ovelap using Moore Model
Seq. detector using Mealy Model non-overlapping type
new concept
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Exp
Note On The Increasing Counter: It’s like increasing decimal numbers, say we have 273, we add one to the Least Significant Decimal, 274, do this till 279, then we move to the next decimal and zero the LSD, 280. In the decreasing counter, we do this from the end to begining, in the schema, we start with 1111, subtract 1 from it, we’d have 1110, subtract another 1, 1101, so on….
A bit toggles at the next clock after all its less significant bits are 0. I.O.W when they all toggle from 0 to 1
Note On Option 1: TA is always 1 because it toggles by every clock.
2
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Note On CLK shape: It’s sensitive to the rising edge. look at the dotted lines drawn.
Note On How It Works: the starting state is “a”, the input at first is “0” then comes the clock signal, when this signal comes, if we have a change in the input, we can potentially change the state (we may not, for example the 2nd and 3rd clock the input is 1 so it stays in b), so on… When the clock has a rising edge, we look at the input signal and the state we’re in to determine the next state
Note On state d: In state d with input 1 output is 1 and with 0 output is 0 so the output takes the form of the input. this is how we distinguish between opt 2 and opt 3
1
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Note: In Moore models, the output is in sync with the clock, so the output doesn’t change between the edges (two clocks). just by knowing this we choose 1
Note On Solving: We move forward and when we get the clock pulse, by looking at the state we’re in and input we find the next state (This part is similar to Mealy) BUT we use the state only to find the output, input has no role in it (Unlike Mealy in Q9 ,where d was 1 with input 1 and 0 with input 0, so we knew it mimics the input when we’re in this state)
This type of Qs can be time consuming to solve
4
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Note On Periodic State: A circuit has a warmup state and a periodic one after that.
Note On D flip-flop: A D flip-flop is a type of digital electronic circuit used to delay the change of state of its output signal until the next rising edge of a clock timing input signal occurs. The basic working of the D flip-flop is that when the clock signal is low, the flip-flop holds its current state and ignores the D input. When the clock signal is high, the flip-flop samples and stores the D input. The value that was previously fed into the D input is reflected at the flip-flop’s Q output. (so the output shows what’s been stored in D from the previous clock)
Note On Option 1: hang up is when there are two different cycles and we can’t go from one to another (if we didn’t have 5 to 4 in the schema and had 7 to 6 instead).
Note On Option 3: A Linear-feedback shift register (LFSR) is not a DFA (Deterministic Finite Automaton) since it randomly generates numbers, so the next state is not deterministic.
Note On the seq. writing: We write the seq.s using the equations, till we reach a repeat seq. which we then remove the new seq. and move back to the original one (the first time the repeat seq. was shown).
Note On Finding The rest of the seq.s: we have 3 bits therefore 8 possibilities, we started from 000 and drew 5 so 3 remains, we draw them to see where they end up.
Note On Option 4: self start means no matter where we begin, we eventually fall in the cycle (the drawn schema). the cycle consists of numbers 3,5,6. and we don’t have hang up.
3
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Note On Asynchronous Circuits: The clock for the Q2 is different from the other two.
Note the clock terminal is active low, so the clock pulse is the falling edge so when Q1 goes from 1 to 0, Q2 toggles.
Best Solution is differentiating between the options: for example we don’t try 0 because they all go from 0 to 2, here we choose 6. then to choose between opt 1 and 3, we use 2.
2
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Note On The Register: At first it’s all 0s, and Ds mean D-flipflop. they make Z=0 and A=0 in the Adder B is always 0, carry in=1 so it outputs 1 so 1 is stored in the register, when the CLK signal comes, the first D-flipflop outputs 1and the rest are 0, this cycle repeates, Z=0 then etc. till all the 7 bits of the register are 1, which gives the number 255, then Z=1, then Sel 1 (80) goes to the register then goes to the Adder (+ carry=1) then we’d have 81 in the registern, then again Z=0 and 82 goes in the register, till it’s 255 again.
Note On Frequency: for every 176 clocks z becomes 1, so op3 is correct.
Note On Warm up Stage: It’s the first part where register goes from 0 to 80 and enters the preiodic cycle.
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Note On Gray Counter: it goes from 00 to 01 to 11 to 10 to 00 again. (like k-map) in the drawn table, the first column is binary count, the second one is the gray count.
Note: We can put the a truth table row in the options and check.
The * on top means the next state for y0 or y1
Note that we chose groups with a fixed value of y0* and y1* in their respective tables
The K-maps are drawn for Ms and y1y0 states, the values are y1* in one table and y0* in another. BASICALLY we’re trying to find the equation for the next y1 and y0 bits using two separate K-maps
