1.1 S. Architecture

Question 1

ADDRESS BUS function and properties:

Answer 1

• transmit memory addresses specifying where data is to be sent to/retrieved from
• uni-directional

Question 2

what determines the max. memory addresses in the bus?

Answer 2

• the width of the address bus determines the max. possible memory addresses
• a 32-bit AB has the capacity for 2^32 addresses

Question 3

DATA BUS function and properties:

Answer 3

• used for transporting data and instructions between components
  -bi-directiona’

Question 4

what does width determine for the data bus?

Answer 4

• defined by the no. of wires/lines it contains
• when the data bus is the same width as a computer word, data can be transferred to and from the memory in a single action

Question 5

what is the system bus?

Answer 5

• three separate buses carrying control signals, addresses and data

Question 6

memory read control signal?

Answer 6

causes data from the addressed location in RAM to be placed on the data bus

Question 7

memory write control signal?

Answer 7

causes data on the data bus to be written into the addressed location in RAM

Question 8

bus request control signal?

Answer 8

indicates that a device is requesting use of the data bus

Question 9

bus grant control signal?

Answer 9

indicates that the CPU has granted access to the data bus

Question 10

clock control signal?

Answer 10

used to synchronise operations

Question 11

how do buses link to assembly language?

Answer 11

the architecture of a computer eg. word size and width of address bus determines the format of a machine code instruction

Question 12

Arithmetic-Logic Unit (ALU) function:

Answer 12

arithmetic (+, -, *, /), logical (AND, OR, NOT, XOR) and shift (shifting bit series within a register) operations

Question 13

what are registers and why are they useful?

Answer 13

• locations of super-fast memory used to temporarily store results for immediate access and re-use
• this is useful as carrying out a sequence of instructions requires many different pieces of information to be held

Question 14

Program counter (PC):

Answer 14

• holds the memory address of the next instruction to be executed

Question 15

Memory Address Register (MAR):

Answer 15

• holds the address of where the processor must fetch data from or store it to

Question 16

Memory Data Register (MDR):

Answer 16

• temporarily holds data moving between the processor and main memory

Question 17

Current Instruction Register (CIR):

Answer 17

• holds the current instruction, which is split into opcode (the instruction that is executed by the CPU and addressing mode) and operand (the data or memory location used to execute that instruction)

Question 18

Accumulator (ACC):

Answer 18

• holds intermediate results of an instruction

Question 19

opcode

Answer 19

the instruction that is executed by the CPU and addressing mode

Question 20

operand

Answer 20

the data or memory location used to execute that instruction

Question 21

fetch:

Answer 21

1. address of next instruction is copied from PC —→ MAR
2. instruction held at that address is copied —→ Memory Data Register (MDR)
3. simultaneously, contents of PC are incremented
4. contents of the MDR are copied —→ CIR

Question 22

decode:

Answer 22

1. instruction in CIR is decoded
2. decoded instruction split into operand + opcode to determine instruction type
3. if required: additional data is fetched from memory —→ ACC

Question 23

execute:

Answer 23

1. the opcode is executed on the operand
2. instruction executed and result held in ACC or —→ memory

Question 24

FACTORS AFECTING CPU PERFORMANCE:

Answer 24

• clock speed
• num. cores
• amount and type of cache memory