Trojans

Question 1

Hardware Trojan

Answer 1

A malicious, intentional addition or modification to the existing circuit
elements

Question 2

Using Hardware Trojans to

Answer 2

• Change the functionality (e.g., deactivating authentication or
  encryption)
• Reduce the reliability (e.g., accelerate aging)
• Leak valuable information (e.g., bypassing the side-channel
  protections, providing backdoors, etc

Question 3

Hardware trojan Targets

Answer 3

Vulnerability of chips to add/delete/alterations of
circuit structure or through modification of
manufacturing process steps that causes
reliability issues in ICs in applications such as:
- Defense/military application
- Aerospace applications
- Civilian security-critical security
- Financial applications
- Transportation applications

Question 4

General Structure of a Hardware Trojan

Answer 4

Trigger Logic is responsible for
activation mechanism
- Payload Logic is responsible to the
effect
- A hardware Trojan causes a
malfunction by modifying signal S
to S´
- Activated only under very rare
conditions
- Trojans are stealthy: it evades
detection under conventional postmanufacturing test/validation process.

Question 5

Insertion Phase- Specification phase:

Answer 5

Definition of system’s
characteristics
m For example, a Trojan changes the hardware’s timing
requirements

Question 6

Insertion Phase- Design Phase

Answer 6

Design gets implemented for the target
technology
- Trojans might be in any of the components that aid the
design (third-party IP blocks and standard cells).
- For example, a standard cell library can be tampered
with Trojans
- Insertion during design&raquo_space; HDL level Trojans
- Combinational and Sequential Trojans

Question 7

insertion phase- Fabrication Phase

Answer 7

Creation of mask set
and use wafer to create mask
- Changing dopant concentration to increase the aging
(Time Bombs)
- Modifying dopant polarity
- Modifying the layout=chip functionality
m Insertion during fabrication&raquo_space; Layout Trojans

Question 8

Insertion Phase : Testing phase

Answer 8

Modifying automatic test pattern generators&raquo_space; reduce chance

that trojan gets detected

Question 9

Insertion Phase - Assembly

Answer 9

Assemble components on a PCB
- For example, adding unshielded wire&raquo_space; electromagnetic
coupling&raquo_space; side-channel leakage

Question 10

Abstraction Level- System level:

Answer 10

Trojan can a be triggered by system component,

e.g. by specific ASCII input from keyboard

Question 11

Abstraction Level - RTL level:

Answer 11

Manipulating RTL design, e.g., half rounds of

cryptographic implementation

Question 12

Abstraction Level- Gate level

Answer 12

Trojan consisting of basic gates (AND, XOR, OR) that

monitor the chip’s inner signals

Question 13

Abstraction Level - Transistor level:

Answer 13

insert, remove, change functionality, size&raquo_space; delay and

reliability changes

Question 14

Abstraction Level - Physical level:

Answer 14

change, insert, remove wires&raquo_space; add/remove

connections, change timing

Question 15

Activation Mechanisms

Answer 15

Always on
Triggered
- Internally triggered: time-based or physicalcondition-based; e.g. counter, temperature
threshold
- Externally triggered: triggered by user-input or
component-output

Question 16

Payload

Answer 16

Change functionality
- e.g., a Trojan might cause an
error detection module to accept inputs that
normally should be rejected

 Downgrade performance (power, delay)
- e.g., insert more buffers to drain battery more quickly

Leak information
- covert and overt channels, all kinds of side-channels,
unused ports, e.g. leak cryptographic key

Denial-of-Service
- exhaust resources, destroy device, disable
device/functionality, alter configuratio

Question 17

Location

Answer 17

Random logic

• insertion into synthesized logic portion of the IC
• very hard to detect

Processing unit

• insertion into logic units that are part of a processor
• e.g., change instruction order

Crypto accelerator
- e.g., leak sensitive information, compromise security, replace
keys

Memory units
- alter content stored in memory

I/O ports
- control over communication

Power supply
- alter voltage, e.g., to cause failures

Clock grid
- e.g., glitches, fault attacks, halt clock

Question 18

Trojans in Cryptographic Engines

Answer 18

A Trojan that attempts to leak a secret key from inside a
cryptographic IC through power side-channels using a
technique called malicious off-chip leakage enabled by side
channels (MOLES)

• Another possibility: The payload could be a mechanism that
  presents dummy keys, predefined by the attacker

Question 19

Trojans in General-Purpose Processors

Answer 19

• An attacker at the fabrication facility can implement a
  backdoor, which can be exploited in the field by a software adversary.
• The attacker at an untrusted fabrication facility could
  implement a backdoor which disables the secure booting
  mechanism under certain rare conditions or when
  presented with a unique rare input condition in the hands
  of an end-user adversary

Question 20

Hardware Trojan Designs

Answer 20

HDL level Trojans&raquo_space; Insertion during design
-Combinational and Sequential Trojans

Layout Trojans&raquo_space; Insertion during fabrication

• Changing dopant concentration to increase the aging (Time Bombs)
• Modifying dopant polarity
• Modifying the layout=chip functionality

Question 21

HDL Level - Combinational Trigger

Answer 21

Activation depends on the occurrence of a particular
condition at certain nodes of the circuit (here A = 0
and B=0)

Question 22

HDL Level - Sequential Trigger

Answer 22

• Activation depends on the occurrence of a specific
  sequence of are logic values at internal nodes (timebomb)
• Synchronous k-bit counter which activates when the
  count reaches 2k−1

Question 23

HDL Level - Asynchronous Trigger

Answer 23

Sequential Trojan independent of the system Clock:
- the count is increased not by the clock, but by a rising
transition at the output of an AND gate with inputs
p and q

Question 24

HDL Level - Hybrid Trigger

Answer 24

• Combination of combinational and sequential Trojans: counts
  of both a synchronous and an asynchronous counter
  simultaneously determine the Trojan trigger condition
• More complex state machines of different types and sizes can
  be used to generate the trigger condition based on a
  sequence of rare events

Question 25

HDL Level - Analog Trigger

Answer 25

An analog trigger mechanism where the inserted capacitance
is charged through the resistor if the condition q1= 1, q2= 1
is satisfied, and discharged otherwise, causing the logic
threshold to be crossed after a large number of cycles.

Question 26

Analog payload

Answer 26

• A bridging fault is introduced using an inserted resistor
• The delay of the path is affected by increasing the
  capacitive load.

Question 27

Analog trigger

Answer 27

Using the dedicated temperature sensors on the chip to

trigger the payload!

Question 28

Layout Level - Stealthy Dopant-Level Trojan

Answer 28

- Changing the dopant of
NMOS and PMOS
transistors
- Example: Changing the
dopant of an Inverter to
give out always “1” or “0”
independent of its input
- Successful implementation
on Intel Ivy Bridge’s RNG
and establishing hidden
side channels for AES

Question 29

Layout Level - Diffusion Programmable

Device (DPD)

Answer 29

Changing the dopant of
SRAM cells to manipulate
the LUT output to
constant values

Question 30

Pre-Silicon Trojan Detection Methods

Answer 30

Code-Coverage analysis
-Completeness of functional verification, identify suspicious signals, validate
trustworthiness of third-party-IP
- e.g., remove unused circuit paths

Formal verification
- e.g., formal proof provided by 3rd party vendor, integrator validates proof

Logic testing using simulation
-Apply different input patterns to activate the trojan

Functional analysis using simulation

• Apply random input patterns
• Try to find “nearly-unused logic”

Question 31

Destructive Post-Silicon Trojan Detection

Answer 31

Use reverse-engineering to depackage the IC and get
images of each layer of the chip
r&raquo_space; Reconstruct the design and do validation
- Using Scanning Electron Microscope with a golden chip
- Comparing optical images of different chips with layout reveal “the”
additional wires and transistors
- Advantage: - Can find inactive trojans
- Disadvantage: - Expensive and time consuming
- Hardware gets unusable
- Need golden chip