1.1.1 Structure and Function of the Processor Flashcards

(39 cards)

1
Q

What is the function of the CPU?

A

Executes instructions using the Fetch-Decode-Execute (FDE) cycle.

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2
Q

What are the components of the CPU?

A

Arithmetic Logic Unit (ALU), Control Unit (CU), Registers, Buses.

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3
Q

What does the ALU do?

A

Performs arithmetic and logical operations.

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4
Q

Where are the results of ALU calculations stored?

A

In the Accumulator (ACC).

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5
Q

What does the Control Unit (CU) do?

A

Directs CPU operations, manages data flow, decodes and executes instructions.

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6
Q

What synchronises CPU operations?

A

The clock.

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7
Q

What are registers in the CPU?

A

High-speed, small storage locations.

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8
Q

What is the function of the Program Counter (PC)?

A

Holds the address of the next instruction.

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9
Q

What is the function of the Accumulator (ACC)?

A

Temporarily stores results of ALU operations.

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10
Q

What is the function of the Memory Address Register (MAR)?

A

Stores the address to read/write from/to.

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11
Q

What is the function of the Memory Data Register (MDR)?

A

Temporarily stores data read from/written to memory.

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12
Q

What is the function of the Current Instruction Register (CIR)?

A

Holds the current instruction (opcode + operand).

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13
Q

What are General Purpose Registers (GPR)?

A

Temporarily store data during execution.

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14
Q

What are buses in a CPU?

A

Set of parallel wires that transfer data/signals.

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15
Q

What are the three types of system buses?

A

Data bus, address bus, control bus.

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16
Q

What does the data bus do?

A

Bi-directional. Carries data/instructions.

17
Q

What does the address bus do?

A

Carries memory addresses (from MAR to RAM).

18
Q

What does the control bus do?

A

Carries control signals like memory read/write, clock, interrupt.

19
Q

What are the steps of the Fetch-Decode-Execute cycle?

A

Fetch, Decode, Execute.

20
Q

What happens in the ‘Fetch’ step?

A

PC → MAR, instruction to MDR, PC incremented, MDR → CIR.

21
Q

What happens in the ‘Decode’ step?

A

CIR is split into opcode and operand, decoded by CU.

22
Q

What happens in the ‘Execute’ step?

A

Instruction is executed (e.g. via ALU or data transfer).

23
Q

What affects CPU performance?

A

Clock speed, number of cores, cache memory, pipelining.

24
Q

What does clock speed control?

A

Rate of instruction execution (Hz).

25
What is overclocking?
Increasing clock speed, produces more heat.
26
How do multiple cores affect performance?
Allow simultaneous instruction execution.
27
What is cache memory?
Very fast, small memory storing frequently used data/instructions.
28
Describe L1 cache.
Fastest, smallest (2–64 KB).
29
Describe L2 cache.
Larger, slower than L1 (256 KB–2 MB).
30
Describe L3 cache.
Even larger and slower, shared across cores.
31
What is pipelining?
Overlapping multiple instructions during the FDE cycle.
32
What are the types of pipelining?
Instruction pipelining and arithmetic pipelining.
33
What is the Von Neumann architecture?
Single memory for data and instructions, simpler and cheaper.
34
What is the Von Neumann bottleneck?
Slower data transfer compared to CPU speed.
35
What is the Harvard architecture?
Separate memory and buses for data and instructions.
36
Where is Harvard architecture used?
In embedded systems (e.g. digital watches, microwaves).
37
What architecture do contemporary processors use?
Von Neumann for main memory, Harvard for internal cache.
38
What is assembly language?
Low-level language using mnemonics.
39
What are the parts of an assembly instruction?
Opcode and Operand.