1.1.1 Structure and Function of the Processor Flashcards
(12 cards)
Control Unit Jobs
Coordinates activies of the CPU
Manages flow of data between CPU and other devices
Accepts the next instruction
Decodes instructions
Stores the result in the memory
Registers
CIR: Holds the current instructions being executed, divided up into operand and opcode
Factors affecting performance
Clock Speed:
() Processor activities behin on a clock pulse
() Starts as clock changes from 0-1
() Clock speed is number of clock cycles per second
Number of cores:
() A core is an independent processor able to execute its on FDE cycle
() Some programs arent optimised for this
Amount of cache
() CPUs onboard memory
() Stores frequently used instructions
Buses
Set of parallel wires which connect two or more components inside the CPU
System bus: Collection of data bus, control bus, address bus
FDE cycle
PC: Value -> MAR -> Address bus -> RAM -> Data Bus -> MDR -> CIR: Split into opcode and operand -> CU -> ALU -> ACC
ALU Components:
Arithmetic Circuit
Logic Circuit
Registers (To store data)
Flags: Overflow, zero
What happens in execute based on instruction:
INP: ACC stores the value
OUT: Value already in ACC
STA: Reverse: ACC -> MDR -> RAM
ADD / SUB: Result stored in ACC
Pipelining
Concurrent processing of multiple instructions
One instruction fetched while other decoded and another executed
Output of one is input of next
Pipelining Benefit:
More instructions executed
Quicker for program to complete
Von Neumann vs Havard:
Data and instructions stored in the same memory
Single set of buses for instructions and data
Harvard Architecture Advantages:
Instructions and data can be accessed concurrently
Less chance of data corrupttion
Higher memory bandwidth
Contemporary Processing
Combo of Havard and Von Neumann architecture.
Harvard is used for cache.
