Computing Architecture Flashcards
1
Q
Fetch stage 1
A
Address copied from PC to MAR.
2
Q
Fetch stage 3
A
The addressed instruction in main memory is returned via data bus to MBR.
3
Q
Decode 1
A
CIR is decoded. Split into opcode and operand.
4
Q
Fetch stage 2
A
The address is sent via the address bus to main memory.
5
Q
Fetch stage 4
A
PC is incremented.
6
Q
Decode 2
A
Extra data is fetched if needed.
7
Q
Execution 1
A
Instruction executed, ALU if necessary, results stored.
8
Q
Execution 2
A
SR updated
