Lecture 2 - ARM Assembly and Input/Output

Question 1

What is an immediate value?

Answer 1

A value that is not stored anywhere, but rather a part of the instruction itself

Question 2

Why can immediate values only be 8 bits?

Answer 2

When looking at the instruction format, the operand 2 field contains bits for immediate value. However, these are only 8 bits and therefor sets the constraint

Question 3

What does the ARM Assembly function bl do?

Answer 3

First sets Link Register (r14) to PC + 4.
PC is the address of the current instruction, in this case the bl instruction itself.
PC+ 4 corresponds to the sequentially next instructions, as each instructions are 32 bits.
Then the bl instruction sets the PC to the label provided with the bl instruction.

Question 4

In ARM Assembly, what happens when you need to return from a function

Answer 4

Need to move LR to PC,LR remembers where the function was called from.

Question 5

In ARM Assembly, what are callee registers?

Answer 5

r4 - r12 are defined as callee saved registers.
If a called function needs to write to any of these registers, it first needs to save these values. And before it returns to the callee function, it needs to restore the values to these registers.

Question 6

In ARM Assembly language, what are caller saved registers?

Answer 6

r0-r3 are defined as caller registers.
parameters are passed in r0-r3.
return values are stored in r0 and r1.
If the caller wants to preserve the values of these registers after a function call, it needs to save these values before the fundtion call, and restore them afterwards.

Question 7

How does the stack operate?

Answer 7

Last-in-First-out

Stack pointer (r13, SP) always points to the last occupied position in the stack

Stack grows downwards.

Push and pop are special instructions to operate on the stack. SP moves automatically with these

pop from stack does not remove values, just moves the stack pointer upwards

Content of stack, growing downwards:
- parameters
- caller context
- return address
- local vars

Question 8

What is CISC?

Answer 8

Complex Instruction Set Computer.

Also known as register-memory architectures

appeared in early computers (i.e. x86)

Computers mostly programmed in assembly - assembly instructions close to what HLL now provide

Few registers - operands in memory, instructions were allowed to operate directly in memory

memory was limited, instructions were of variable length because of this

Question 9

What are the two categories of ISAs?

Answer 9

CISC and RISC

Question 10

What is RISC

Answer 10

Reduced Instruction Set Architecture.

load-store architectures

Appeared in the 80’s

HLL and compilers were already well developed. Because of this the instructions could remain simple

More registers and memory, faster clock.
Because of this fixed length/format instructions were implemented for easy and fast decoding

Question 11

Name four properties of I/O devices?

Answer 11

Device (Mouse, keyboard, network)

Behaviour (Input, output, both, storage)

Partner (human, machine)

Data rate (Mbit / sec)

Question 12

What is an IO controller?

Answer 12

Connects the I/Odevice and the CPU

contains a data- and a status registers.

Different IO devices connects to different IO controllers through different interfaces (video, USB, PCIe)

Question 13

What does the data register in the IO controller contain

Answer 13

For input devices: Holds data read from device

For output devices: Holds data that needs to be written to the device

Question 14

What does the status register in the IO controller contain

Answer 14

status of read/write operation

Question 15

How is IO devices addressed?

Answer 15

Memory mapped I/O
Isolated I/O space

Question 16

What is memory mapped I/O?

Answer 16

I/O controller registers are mapped to dedicated portion of memory

Upside: can use regular load/store ops for this

Downside: eats up memory space

Question 17

What is isolated I/O space?

Answer 17

I/O devices are in a completely seperate memory space.

One memory address can both belong to a space in memory and an I/O device

Because of this, seperate instructions are used to communicate with these addresses to differentiate when you are communicating with memory or when you are communicating with I/O

Question 18

What are the methods the CPU uses to determine if an I/O device is ready for data transfer?

Answer 18

Polling (busy-wait I/O)
Interrupt

Question 19

What is polling (busy-wait I/O)?

Answer 19

CPU monitors I/O continuously to see if it’s ready.

This wastes CPU time, but makes CPU react fast when ready

Question 20

What are interrupts?

Answer 20

The I/O controller sends an interrupt signal to the CPU when the device is ready

Slow response from CPU as CPU must finish what it was doing before it can handle the interrupt

Better CPU utilization as CPU resources are not wasted

Question 21

What happens on an interrupt?

Answer 21

I/O controller sends an interrupt signal to the CPU

The CPU saves the address of the current instruction (saves state to be able to continue later on)

Jump to interrupt handler

Handle interrupt (service the I/O device, preserve registers)

Return to foregroung program. There is a special instruction to return from interrupt handler.

Question 22

How do you connect more I/O devices to an CPU than there are ports on the CPU?

Answer 22

Connect I/O devices together through OR-gates.
When doing this, the CPU must poll each device to see where an interrupt signal came from.

Can use an interrupt controller that arbitrates CPU access amoung devices

Question 23

What are the 2 methods of finding the correct interrupt handler?

Answer 23

1: Jump to predefined address. Use cause of interrupt (device id) to specify the right handler

2: Vector interrupts: Directly branch to a specific handler based on device.

Question 24

What is an vector interrupt table

Answer 24

A table that contains information of where the interrupt handler is for each possible interrupt

Question 25

What happens when multiple interrupts come at the same time?

Answer 25

Interrupts have a priority. A high priority is handled before a low one. If an interrupt is being handled when a new one comes, it will continue with the current interrupt if the new one has lower priority. If the new one has higher priority it will interrupt the handler and start handling the new one. When finished, the old one is continued.

Question 26

What does a priority registry store?

Answer 26

The priority of the interrupt currently being executed

Question 27

What does it mean when the CPU masks an interrupt?

Answer 27

When the CPU is doing something important, the CPU won’t be informed that an interrupt has occured of lower priority

Question 28

What are NMIs and what do they do?

Answer 28

NMI’s, or non-maskable interrupts are interrupts that are used when accessing important resources from the CPU

Question 29

Name everything that happens when an interrupt is raised

Answer 29

I/O: raises interrupt

CPU: Checks pending interrupts every cycle. Acknowledges the highest priority interrupt

I/O device: Sends its interrupt vector number to the CPU on receiving acknowledgement

CPU: Saves state (PC, registers), jumps to handler

Software: Performs required I/O operation, might need to save additional CPU state

CPU: Restores state and PC and returns to previous execution

Question 30

Compare exceptions and interrupts

Answer 30

Similar:
- cause CPU to break out of execution
- Handled the same way as interrupts
- Vectored and prioritized

Differences:
- Raised by internal error during program execution
- Caused by invalid condition, illegal memory access, …

Question 31

What are traps

Answer 31

Traps are explicitly generated and requested by programmer.
Generated by special instructions.
Not raised because of errors, as exceptions are.

Used to request OS services

Question 32

What is a Bus?

Answer 32

Collection of wires running between components

It is also the protocol that determine how two devices communicate

Question 33

Name 3 bus signals

Answer 33

Address bus: n wires that specifies an address, often unidirectional going from the CPU to memory.

Data bus: n wires that carry data, bidirectional

Control bus: wires to implement bus protocol (read/write, interrupts). Often bidirectional but most individual wires (control signals within the bus) are unidirectional.

Question 34

How does communication happen over a bus? (4 stage handshake protocol)

Answer 34

When two devices communicate, one will send a request and the other answers with an ack.

Device 1 raises an enquiry signal.
Device 2 sends the 2 when ready to listen
Data transfer happens.
When the data transfer is finished, one device lowers its signal.
The other terminates operation.

Question 35

What is an asynchronous bus?

Answer 35

Events can happen at any time

Question 36

How does read and write happen on a synchronous bus?

Answer 36

Events are synchronized with a clock signal.
Events can only happen on the rising or the lower edge of the clock.

Question 37

What are wait states?

Answer 37

When devices are not able to provide data at the next clock cycle, there are cycles where there are no activity.These are wait states.

Question 38

What are burst transfers?

Answer 38

When more data is provided than can be transported in one cycle on the bus.
When this happens one request is sent, and the data is transfered during the next cycles until all data has been transferred.

Question 39

What is direct memory access?

Answer 39

When data is transferred directly to memory without involving the CPU.

A component named the DMA controller, which is much simpler than the CPU,
will instead handle this data transfer.

During this, the memory bus won’t be accessible to the CPU which in the meantime only can do computations on data in registers and caches. If the CPU is dependent on memory that is not in caches, it waits for the memory bus to be available.

Question 40

How can we reduce CPU wait cycles when memory bus is taken by the DMA?

Answer 40

Limit data (just a few words) in the DMA transaction before giving control back to the CPU that checks if it need any memory.
The DMA will request the bus back using the Bus request signal. CPU gives DMA access by enabling bus grant signal.