2.3 2.4 Combinatorial Logic Flashcards
What is the decomposition design pattern
Separate function for each output bit
What is the sharing design pattern
If value used twice, only compute it once and share value.
What is the isolated replication design pattern (2-input 1-bit to 2-input m-bit AND gate)
Replication of gates
What is the cascaded replication design pattern (2-input 1-bit to n-input 1-bit AND)
Cascade ANDs together
What is the algorithm for computing a Karnough map expression
- OR true conditions together (DNF)
- 2^i groups
What is the difference between a multiplexer and demultiplexer
Mux: choose between input signals
Demux: choose between output wires (to send input)
What is the multiplexer circuit diagram (and truth table)
What is the demultiplexer circuit diagram (and truth table)
How can you chain multiplexers via isolated replication (ie propagate entire word)
How can you chain multiplexers via cascaded replication (ie multiple decision points)
What is the difference between a half and full adder
What is a half adder circuit diagram
What is the full adder circuit diagram
What is the n-bit addition circuit (FA)
What are the 2 essential comparison operators
- EQ, LESS THAN
What is the equality comparitor circuit and truth table (1-bit)
What is the less than comparator circuit and truth table (1 bit)
What is the n-bit equality circuit
- Cascaded replication
What is the n-bit less than comp circuit
