Architecture 08

Question 1

What is MIPS32?

Answer 1

A RISC ISA with 32 32-bit general purpose registers (r0..r31)

Question 2

What are the MIPS32 conventions for register purpose?

Answer 2

r0 = $zero = 0
r29 = $29 = $sp (stack pointer)
r30 = $30 = $fp (frame pointer)
r31 = $31 = $ra (return address)
$hi/$lo = result of multiplication/division

Question 3

Past Paper Question: In the MIPS32 instruction set architecture, name the 3 general types of instruction format. For each one, briefly describe what fields each 32 bit instruction contains

Answer 3

R-type
• Arithmetic and logic instructions
• Instruction contains 3 registers
I-type
• Load/store or branch instruction
• Instruction contains 2 registers and 1 immediate address
J-type
• Jump instruction
• No registers, only immediate address

Question 4

For I-type instructions, what can the immediate address be?

Answer 4

• A displacement for a register (index mode)

* An immediate value (immediate mode)

Question 5

Past Paper Question: Name the five stages in the MIPS processor pipeline and briefly describe what each does.

Answer 5

IF (Instruction Fetch)
• Fetch the next instruction
ID (Instruction Decode)
• Decode the instruction and fetch operands from registers
EX (Execute)
• Perform the arithmetic/logic operation specified by the opcode
MEM (Memory)
• Perform memory read or write, if needed
WB (Write Back)
• Store the result back to the registers

Question 6

Past Paper Question: What is the pipeline in a CPU?

Answer 6

A hardware configuration which means the results from one hardware unit are passed to the next hardware unit. In MIPS, there is a 5-stage pipeline and at any time the pipeline contains 5 instructions.

Question 7

Past Paper Question: Briefly describe each of the following three types of pipeline hazard: structural hazard, data hazard, control hazard.

Answer 7

Hazards arise due pipeline stalling, caused by delays in instruction execution
• A structural hazard is when two tasks can’t be completed simultaneously because they need the same hardware
• A data hazard is when the output of one instruction is the input to another
• A control hazard is when a conditional branch changes which instructions should be executed

Question 8

Past Paper Question: Briefly explain the term forwarding, and what problem related to the pipeline it solves

Answer 8

• When ID hardware notices a data hazard, set up a direct connection between ALU outputs and inputs
• Uses a relevant value in the next instruction at the same time as it is written to destination register

Question 9

Past Paper Question: Briefly explain the term branch prediction, and what problem related to the pipeline it solves

Answer 9

• When the processor predicts the output of a conditional statement and executes one block of code as opposed to both outcomes
• It looks for a condition being the same value over and over again for example in a loop, then assumes the same result.

Question 10

Past Paper Question: Briefly explain the term out-of-order execution, and what problem related to the pipeline it solves

Answer 10

• An instruction fetched and dispatched to a queue, then waits until its input operands are available
• If the operands are available it can leave the queue before older instructions
• The instruction is carried out then the result is put in queue with other results, which are popped in order

Question 11

What is meant by the term scalar processor?

Answer 11

Even with pipelining we can still only execute one instruction per cycle

Question 12

What is meant by the term superscalar?

Answer 12

A processor has different EX units, so one could execute different instructions simultaneously if they don’t require the same EX unit. If you were to do them simultaneously on different EX units, IF and ID stages need to be duplicated

Question 13

What is meant by hyper threading?

Answer 13

Utilising idle parts of a processor by making the os think there are twice as many processors as there actually are, which avoids many hazards