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ECE150 (Mobile Embedded Systems) > Application Processor Part 1 > Flashcards

Application Processor Part 1 Flashcards

1
Q

What is the Arithmetic/ Logic Unit?

A

Operate on values stored in the Registers

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2
Q

What is a register?

A

Group of flip-flops with common clock used to store binary data

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3
Q

What is the instruction register?

A

Hold current instruction.

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4
Q

What is the instruction pointer?

A

Hold the address of the next instruction in memory

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5
Q

What is RISC?

A

Reduced Instruction Set Computer. Only execute one instruction at a time but usually take one machine cycle.

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6
Q

What is CISC?

A

Complex Instruction Set Computer. Executes an instruction over a span of two to ten machine cycles but can execute multiple steps of each instruction at the same time.

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7
Q

What is the CORTEX A series used in?

A

Smartphones, digital TV, servers and networking.

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8
Q

What is the CORTEX R series used in?

A

Automotive Braking systems, powertrain solutions, and mass storage controller.

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9
Q

What is the CORTEX M series used in?

A

Micro controllers, mixed signal devices, and smart sensors

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10
Q

What are the main features of ARMv7 A architecture?

A
  • Large uniform register file
  • 32 bit processor
  • Instructions are 32 bit long
  • Good speed/power consumption ratio
  • High code density
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11
Q

What are the enhancements to basic RISC features?

A
  • Control over ALU and shifter for every data processing operation to maximize there usage.
  • Auto-increment and auto-decrement addressing modes to optimize program loops
  • Load and store multiple instructions to maximize data throughput
  • Conditional execution of instruction to maximize execution throughput.
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12
Q

What does the ARM Core Registers do?

A
  • The general purpose registers hold either data or address.
  • All registers are 32 bits
  • In user mode 16 data registers and 2 states registers are visible
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13
Q

What is the function of register r13?

A

Stack pointer (can also be used as GPR)

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14
Q

What is the function of register r14?

A

Link register (where return address is put whenever a subroutine is called and can be used as GPR)

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15
Q

What is the function of register r15?

A

Program counter

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16
Q

What are the two status registers?

A
  • CPSR : current program status register

- SPSR : saved program status register

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17
Q

What are the flags of CPSR?

A
  • Condition code flags
  • Sticky overflow flag
  • J bit
  • Interrupt disable bits
  • T Bit
  • Mode bits
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18
Q

What are the flags of condition code flags?

A
  • N : Negative result from ALU
  • Z : Zero result from ALU
  • C : ALU operation Carried out
  • V : ALU operation oVerflowed
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19
Q

What does flag N of condition code flags do?

A
  • Logical Instruction : No meaning

- Arithmetic Instruction : Bit 31 of the result has been set. Indicates a negative number in signed operations

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20
Q

What does flag Z of condition code flags do?

A
  • Logical Instruction : Results in all zeros

- Arithmetic Instruction : Result of operation was zero

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21
Q

What does flag C of condition code flags do?

A
  • Logical Instruction : After Shift operation ‘1’ was left in carry flag
  • Arithmetic Instruction : Result was greater than 32 bits
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22
Q

What does flag V of condition code flags do?

A
  • Logical Instruction : No meaning
  • Arithmetic Instruction : Result was greater than 31 bits. Indicates a possible corruption of the sign bit in signed numbers
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23
Q

What does the processor mode determines?

A
  • Which registers are active

- Access rights to CPSR register itself

24
Q

What is privileged and non-privileged?

A

Privileged : full read-write access to CPSR

Non-privileged : only read access to the control field of CPSR but read-write access to the condition flags.

25
Q

What are the basic operating modes?

A
  • User
  • FIQ
  • IRQ
  • Supervisor
  • Abort
  • Undef
  • System
26
Q

What does User mode do?

A

Unprivileged mode under most tasks are run

27
Q

What does FIQ mode do?

A

Entered when a high priority (fast) interrupt is raised

28
Q

What does IRQ mode do?

A

Entered when a low priority (normal) interrupt is raised

29
Q

What does Supervisor mode do?

A

Entered on reset

30
Q

What does Abort mode do?

A

Used to handle memory access violations

31
Q

What does Undef mode do?

A

Used to handle undefined instructions

32
Q

What does System mode do?

A

Privileged mode using the same registers as user mode

33
Q

What is Banked Registers?

A
  • 20 registers are hidden from program at different times
  • Available in certain modes
  • Maps one-to-one onto a user mode register
34
Q

What is the saved program status register (SPSR)?

A
  • SPSR is associated with privileged mode except system mode

- Used to save the state of CPSR when the privileged mode is entered

35
Q

What is mode changing?

A
  • By writing directly to CPSR or by hardware when the processor responds to exception or interrupt
  • To return to user mode a special return instruction is used that instructs the core to restore the original CPSR and banked registers
36
Q

What is included in the ARM instructions set?

A
  • Data processing instructions
  • Data transfer instructions
  • Block transfer instructions
  • Branching instructions
  • Multiply instructions
  • Software interrupt instructions
37
Q

What is data processing?

A 
Manipulate data
- MOVE instructions
- Arithmetic instructions
- Logical instructions
- Comparison instructions
Suffix S on data processing instructions updates flags in CPSR
38
Q

How does data processing instructions work?

A
  • Operands are 32 bit wide; come from registers or specified as literals in the instruction itself
  • Second operand sent to ALU via barrel shifter
  • 32 bit result placed in register; long multiply instruction produces 64 bit result
39
Q

What is move instruction?

A

MOV Rd, N
- Rd: destination register
- N: can be an immediate value or source register
- mov r7, r5
MVN Rd, N
- Move into Rd not of the 32 bit value from source

40
Q

What does the barrel shifter enables?

A
  • Enables shifting 32 bit operand in one of the source registers left or right by a specific number of positions within the cycle time of instruction
  • Shift left, shift right, rotate right
  • Facilitates fast multiply, division
41
Q

What is arithmetic instruction?

A

Implements 32 bit addition and subtraction

  • SUB r0, r1, r2
    • Subtract value stored in r2 from that of r1 and store in r0.
42
Q

What is arithmetic instruction with barrel shifter?

A

Increases the set of possible available operations

43
Q

What are multiply instructions?

A

Multiply contents of a pair of registers - generate 64 bit results

44
Q

What is multiply and accumulate?

A 
Result of multiplication can be accumulated with the content of another register.
Signal processing
 - Filtering
 - Communications
 - Error control codes
45
Q

What is Logical Instructions?

A

Bit wise logical operations on the two source registers.

46
Q

What is compare instructions?

A

Enables comparison of 32 bit values, update CPSR flags but do not affect other registers

47
Q

What is data transfer instructions?

A
  • Load/store instructions

- Used to move signed and unsigned Word, Half Word and Byte to and from registers

48
Q

What is Multiple Register Transfer?

A
  • Load-store multiple instructions transfer multiple register contents between memory and the processor in a signal instruction
  • More efficient for moving blocks of memory and saving restoring context and stack
  • Increase interrupt latency
49
Q

What are block transfer instructions?

A
  • Load/store multiple instructions (LDM/STM)

- Whole register bank or a subset copied to memory or restored with single instruction

50
Q

What is swap instruction?

A

Exchanges a word between registers.

- Two cycles but single atomic action

51
Q

How to modify status registers?

A
  • Indirectly
  • MSR moves contents from CPSR/SPSR to selected GPR
  • MRS moves contents from selected GPR to CPSR/ SPSR
  • Only in privileged mode
52
Q

What are control flow instructions?

A
  • Branch instructions
  • Conditional branches
  • Conditional execution
  • branch and link instructions
  • Subroutine return instructions
53
Q

What is branch instruction?

A
  • B label : address label is stored in the instruction as a signed pc-relative offset
  • B : Branch has a condition associated with it and executed if condition codes have the correct value
54
Q

What is conditional execution?

A

The conditional execution applies not only to branches but to all ARM instructions.
- Each data processing instruction prefixed by condition code - 16 conditions

55
Q

Data Processing Instructions overview?

A

Conditional codes + data processing instructions + barrel shifter = powerful tools for efficient coded programs

56
Q

What are the features of ARM instruction set?

A
  • Load/Store architecture
  • 3 address data processing instruction
  • Conditional execution
  • Load/store multiple registers
  • Shift and ALU operation in single clock cycle.

ECE150 (Mobile Embedded Systems) (12 decks)

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