8-10A: Circuits 2

Question 1

8-10A1

ln the circuit shown in Fig.8A4, U5 pins 1 and 4 are high and both are in the reset state. Assume one clock cycle occurs of Clk A followed by one cycle of Clk B. What are the output states of the two D-type flip flops?
A. Pin 5 low, Pin 9 low.
B. Pin 5 high, Pin 9 low.
C. Pin 5 low, Pin 9 high.
D. Pin 5 high, Pin 9 high.

Answer 1

ANSWER D
Pins 1 and 4 do not have an effect on the logic conditon. At the start, pins 5 and 1 are low, and pins 6 and 8 are high. One clock cycle of Clk A causes pins 5 and 12 to take the state of the D input on pin 2, a high. Pins 6 and 2 go low with no effect. On the clock cycle at Clk B, pin 9 iakes the state of 12, which is high.