Sequential Logic

Question 1

RS latch

Answer 1

• fundamental unit for static memory - stores last output (1 bit)
• bi-stable circuit (meaning it can happily exist in either of two stable states, wie eine Wippe)
• ability to “store” its last output. Called a “latch” because it can “latch” onto incoming data
• Logic/Value maintained because feedback path
• Q and Not Q always need to oppose otherwise RS latch invalid

Question 2

D-latch

Answer 2

• Controls what inputs can reach the RS Latch to be stored
• Prevents RS illegal action
• provides a way to latch the Q and not-Q outputs without regard to the status of S or R, we can eliminate one of those inputs to create a multivibrator latch circuit with no “illegal” input states
• If WE=1, then Q FOLLOWS D, but it will only hold on to the “last” D when WE goes from 1 to 0
• When WE = 0, D can still change but Q does NOT FOLLOW it, it is being ignored

Question 3

Clock

Answer 3

acts as the “heartbeat” of our system, creating “windows” of time to write or read to/from our storage devices; acts like a “conductor” to synchronize information windows across our CPU

Question 4

D Flip Flop

Answer 4

An “edge-triggered” device that stores data at the “edge” of the clock. The D flip-flop takes a clock input (often denoted with triangle).
Output only accepts new data when CLK transitions from 0 to 1

Question 5

D Latch vs. flipflop

Answer 5

latch is “level sensitive” and flipflop is “edge sensitive.”

For a Dlatch, windows of time to store/read information are equal
■ When the WE is “HIGH,” Dlatch is open, Q follows D.
■ When the WE is “LOW,” Dlatch is closed, data is stored and readonly.
■ We prepare what we wish to store right before latch closes.

○ For a DFF, the window of time for storage is shorter but we have more time to read.
■ We can only store data in the DFF when the clock transitions from 0 to 1 (note: negativeedge flipflops
also exist).
■ Otherwise, the DFF is closed and we can only read from it.
■ We prepare what we wish to store right before the positive edge of
the clock.

Question 6

Finite State Machine

Answer 6

○ A “machine” that can be built using combinational and sequential logic gates.
○ The “machine” one can only be in a finite # of states.
○ A CPU is a complicated example of an FSM with many states.
■ A toaster is an example of an FSM with two basic states (off and on/warming).
■ Most electronic machines are examples of FSMs.
○ FSMs consist of 3 basic parts:
■ An Nbit register which stores the state of the machine
■ A block of logic that computes the next state as a function of the current state and any inputs
■ A block of logic that computes the output based on the current state

Question 7

Computer memory

Answer 7

physical devices capable of storing information temporarily like RAM (randomaccess memory) or permanently like ROM (readonly memory)

Question 8

RAM
SRAM
DRAM

Answer 8

(random access memory): by specifying address, one can read or write to any “drawer” in the memory at random. I can randomly access any location or any drawer at anytime just by presenting different addresses. I don’t have to look through it in a linear fashion, that would be the opposite of Random Access Memory
Static RAM (SRAM) = Fast, Maintains data as long as power applied (6 transistors per bit)
Dynamic RAM (1 transistor per bit)
■ Denser but slower
■ Relies on “capacitance” to store data. Instead of feedback path as in DFF/RS-Latch
■ Needs constant “refreshing” of data to hold charge on capacitor as capacitors leak.

Question 9

ROM

Answer 9

(readonly memory): nonvolatile memory used in computers and other electronic devices to store data permanently; typically used to hold a small program or setting that a computer might rely on for startup.

Question 10

Clock Frequency

Answer 10

The number of cycles per second is the clock frequency measured in cycles per second or “Hertz (Hz).”
○ The clock period refers to the duration of one clock cycle. The period and frequency are inversely related. –> Long Period, low frequency

Example clock frequency: 2.5GHz = 2.5 x10^9 Hz
■ Corresponding clock period = 1/(2.5 x 10^9 ) = .4x10^9 sec
■ That would be 0.4 nanoseconds.

Question 11

Register

Answer 11

Collection of D Latches or DFF controlled by common WE

Stores a number of bits as a group/unit

Question 12

Address Space

Answer 12

Number of locations
‘Drawers’
Usually a power of 2

Question 13

Addressability

Answer 13

Number of bits per location

‘Width of drawer’

Question 14

What does a n-bit address line mean?

Answer 14

We have n bits to address/label the different drawers. i.e. a n-bit address line can address 2^n drawers
A.k.a. Word (Select) Line.

Question 15

Decoder

Answer 15

n inputs (Address Lines)
2^n outputs (Addresses / Drawers)
At any given point, only one of the 2^n outputs is equal to 1
Only one drawer is opened at any given point in time
Does not store any information

Question 16

Memory Hierarchy

Answer 16

1. CPU (Reg File = small piece of SRAM , fast)
2. Cache Memories: Access times single clock cycles. Storage in MB. (Can be inside CPU or outside). Several Cycles slower than Reg. File.
3. Main Memory (RAM): Access times 10s of clock cycle. Storage in GB, slower and denser. Usually DRAM
4. Disks (Magnetic, Flash etc.) Access time 1000s of clock cycles. Storage in TB.

1-3 looses data if power is switched off
Caches helps mitigate memory delays bw. processor speed and memory speed.
Smaller, faster memory stores are placed closer to the CPU

Question 17

Why can we not build a counter with a D-Latch?

Answer 17

Issue: We need to prepare what we wish to store right before the latch closes. But we can’t guarantee the clock will be low in time to store this new value into the D-latch.
-> Solution: Use DFF

Question 18

Combinational vs. Sequential Logic

Answer 18

Combinational Logic:

• always give the same output for given inputs
• state-less (no memory)

Sequential Logic:

• Output depends on inputs and last output
• forms basis for “state” or “memory” - can hold onto data

Question 19

Logical Structure of Memory

Answer 19

• Address decoder
• Word select line
• Write enable
• bit line / data line
• D-Latches / DFF

Question 20

Memory Address

Answer 20

Reference to a specific memory location used at various levels by software and hardware. They are fixed-length sequences of digits conventionally displayed and manipulated as UNSIGNED integers.

Question 21

What does this mean: Memory addressed by 22 bits and 3 bits addressable

Answer 21

2^22 = # drawers
3 = drawer width

Question 22

One clock cycle

Answer 22

One high (1) one low (0) period

Question 23

Clock Frequency

Answer 23

cycles per second, measured in Hertz

Question 24

Clock Period

Answer 24

Duration of one clock cycle = 1/clock frequency