Basic Types of CPU Flashcards

(21 cards)

1
Q

Basic Types of CPU

According to Instruction Set Architecture:

A
  1. Accumulator-based
  2. General Purpose Register Type
  3. Stack Machine
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2
Q
  • “1-operand CPU”
  • the accumulator is where intermediate arithmetic and logic results are stored
  • early computers were accumulator-based
A

Accumulator-based

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3
Q

Registers in an Accumulator-based CPU:

A
  • A (accumulator)
  • PC (program counter)
  • X (index register) – contains address of memory data
  • SP (stack pointer)
  • Flags register
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4
Q

Convert this to acculumator-based instruction set:

z = (b - c) * d;

A

load b ; A <- [b]
sub c ; A <- A – [c]
mul d ; A <- A * [d]
store z ; [z] <- A

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5
Q
  • The most common type of CPU, Intel 80x86 is of this type but with enhanced/modified features.
  • Other GPR-type CPUs such as PDP-11: 16-bit registers cannot be “divided” into higher and lower bytes.
A

General Purpose Register (GPR) Type

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6
Q

Registers in a GPR Type:

A
  • R0, R1, R2,… R7
  • In PDP-11, R7 is used as PC and R6 serves as SP
  • PC
  • SP
  • Flags
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7
Q
  • 2-address instructions
  • register-memory type:
    each arithmetic instruction has two operands
    destination address is always a register
    source address can be either a register or a memory location
A

GPR Type Instruction Set

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8
Q

Conver this to GPR Type Instruction Set

z = b + c;

A

mov R0, b ; R0 <- [b]
add R0, c ; R0 <- b + c
mov z, R0 ; [z] <- R0

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9
Q

Any computer system that has no general purpose register and simply uses the stack for computations falls on this category.

A

Stack Machine

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10
Q

Registers in a Stack Machine:

A
  • PC
  • X (serves as Memory Address Register for operands)
  • Flags
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11
Q

Convert this to Stack Machine Instruction Set

z = b + c;

A

push b
push c
add ;push(pop() + pop())
pop z

NOTE: arithmetic expressions should first be translated to postfix form to easily write a program for a stack

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12
Q

Basic Types of CPU

A
  1. Accumulator-based - one operand is implicitly the accumulator
  2. GPR-type - all operands are explicitly mentioned, which can be either a register or memory location
  3. Stack machine - the operands are implicitly on top of the stack
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13
Q

Convert this to Stack Machine Instruction Set

z = (b - c) * d;

Postfix: bc-d*

A

push b
push c
sub ; push(pop() - pop())
push d
mul ; push(pop() * pop())
pop z

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14
Q

Accumulator-based instruction set

Data Transfer:

A

load addr ; A <- [addr]
store addr ; [addr] <- A

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15
Q

Accumulator-based instruction set

Arithmetic Operations:

A

add addr ; A <- A + [addr]
sub addr ; A <- A - [addr]
mul addr ; A <- A * [addr]
div addr ; A <- A / [addr]

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16
Q

Accumulator-based instruction set

Logical Operations:

A

and addr ; A <- A and [addr]
or addr ; A <- A or [addr]
not ; A <- not A
not addr ; A <- not [addr]

17
Q

GPR Type Instruction Set

Data Transfer:

A
  • register <- register
    mov dst, src ; dst <- src
  • register <- memory variable
    mov dst, [src] ; dst <- [src]
  • memory variable <- register
    mov [dst], src ; [dst] <- src
18
Q

GPR Type Instruction Set

Arithmetic Operations:

A

add dst, src ; dst <- dst + src
sub dst, src ; dst <- dst – src
mul dst, src ; dst <- dst * src
div dst, src ; dst <- dst / src

19
Q

Stack Machine Instruction Set

Data Transfer:

A

push data ; push immediate
push addr ; push memory var
pop addr ; pop memory var
pop X ; pop an address

20
Q

Stack Machine Instruction Set

Arithmetic Operations:

A

add ; push(pop() + pop())
sub ; push(pop() – pop())
mul ; push(pop() * pop())
div ; push(pop() / pop())

21
Q

Stack Machine Instruction Set

Logical Operations:

A

and ; push(pop() and pop())
or ; push(pop() or pop())
not ; push(not pop())