CH18 Flashcards
(14 cards)
describe what is meant by RISC and CISC processors (4)
RISC; it uses simple instructions with fixed length instructions and makes use of pipelining
CISC; has a large instruction set and requires complex circuits
2 differences between RISC and CISC processors (2)
- RISC has fewer instructions, CISC has many instructions
- RISC uses many registers, CISC uses fewer registers
describe 2 benefits and one limitation of using a virtual machine to emulate a new computer system (3)
benefit 1: new system can be tried on different virtual hardware without need to purchase the hardware
benefit 2: easy to recover if software emulating the new computer system causes crash as VM provides protection to other software
limitation: a virtual machine might not be as efficient because the processing time is increased
describe SIMD
many processors execute the same instruction using different data sets
describe MISD
many processors using different instructions use the same data set
describe MIMD
many process use many instructions using different data sets
describe the process of pipelining during the fetch-execute cycle in RISC processors (4)
- instructions are divided into sub tasks
- each subtask is completed during one clock cycle
- no 2 instructions can execute their same at the same clock cycle
- the 5 stages: IF, ID, OF, IE, WB
what is meant by a virtual machine
the emulation of computer system using a host computer system
state 2 benefits of a virtual machine
- different VMs can be used on the same computer
- cost savings due to not needing to purchase extra hardware
state 2 drawbacks of a virtual machine
- cannot emulate some hardware
- complex to maintain
outline the characteristics of massively parallel computers (3)
a large number of separate computers are connected together creating a network infrastructure and communicating by sending messages
describe the use of pipelining in RISC (2)
- allows several instructions to be processed simultaneously, therefore increasing the number of instructions completed per unit time
describe features of SISD
single instruction, single data architecture. Executes instructions sequentially
describe the features of MIMD
multiple instructions, multiple data architecture and operates independently