Chapter 11: Digital Comms Flashcards
(20 cards)
What problems arise with using schmitt inverter to regenerate a DC signal from AC?
- The thresholds are a fixed percentage of Vs. Noise is not predictable in the transmission.
- Cannot cope with negative Vin
What does a a schmitt trigger do
Regenerates signal and overcomes the problems of a schmitt inverter
What does a schmitt trigger circuit diagram look like
Op amp configured as follows: Vref into inverting, vin into output through 2 resistors, Non-inverting connected in between the two resistors.
When will the schmitt trigger switch to positive saturation?
When the voltage at Vx, where the non-inverting is connected, is above 0V
When will the schmitt trigger switch to negative saturation?
When the voltage at Vx, where the non-inverting is connected, is below 0V
What does the graph of a Schmitt trigger look like
rectangle shaped,centered around Vref.
Symmetrical if Vref=0V
Not symmetrical if Vref≠0V
What is a SIPO
Serial in Parallel out, Shift register. Based off D type flip flops.
SIPO circuit diagram
Common clock and reset. Output from LSB into input of next flip flop and so on. Not Q, not connected.
What is a PISO
Parallel in Serial out shift register
PISO circuit diagram
Common clock, common reset. Logic 0 input to LSB and output into input. AND gate above each flip flop. One input connected to common load, other to individual input.
Loading the PISO
1.D types are reset when first switched on.
2. Data is set up on individual inputs to AND gates.
3. Logic 1 on load to set outputs of flip flop, then back to logic 0.
How is the data shifted on a PISO
1.Clock pulses n times to move the data out of the register of n number of flip flops.
2. MSB outputted first
3. After n pulses, Q outputs are zero
What is PCM
Sampling analogue signals and converting them to binary. Pulse coded modulation
In PCM, what does the sampling gate do?
repeatedly samples the analogue voltage at a frequency determined by the sampling clock.
What does a sampling gate in PCM generate?
A PAM signal that matches the amplitude of the input signal
Describe a PCM transmitter block diagram
- Input
- Low pass filter
- Sampling gate (sampling clock inputted here)
- n bit ADC
- PISO register (piso clock in)
- Output to comms link
In a PCM transmitter what is the value of the sampling clock
greater than or equal to 2x the input frequency
In a PCM transmitter what is the value of the PISO clock
n x sampling frequency/ nyquist
What is the nyquist frequency
The sampling frequency must be greater than 2x the maximum frequency of the info signal
