Chapter 8: Latches and Flip-Flops Flashcards
(43 cards)
1
Q
Digital systems can be classified as either:
A
- combinational
2. sequential
2
Q
Combinational system’s outputs:
A
are completely determined by its present input values.
3
Q
Sequential system’s output:
A
is a function of both its present input values and present state.
4
Q
History is represented:
A
by the binary present state value stored in memory elements in the sequential system.
5
Q
How many states does a memory element have? Specify them.
A
Two:
1
0
6
Q
When a memory element stores a 0:
A
clear
7
Q
When it stores a 1
A
set
8
Q
Synchronous inputs:
A
are inputs whose values can change the memory element’s state only in response to a clock pulse at its clock input.
9
Q
Synchronous input memory:
2
A
- After a memory element has been placed in a particular state, a change in the values of its synchronous inputs cannot change its state until the next clock pulse occurs.
- Tthe memory element stores (remembers) its state value until the next clock pulse.
10
Q
What’s a pulse?
A
A pulse is a shot duration change in a signal’s value.
11
Q
Leading and trailing edge in:
(i) positive-triggered clock
(ii) negative-triggered clock
A
Refer to the final folder inside the FPGA file.
12
Q
Edge:
A
A signal transition is also called an edge.
13
Q
Positive Edge:
A
A transition from 0 to 1 is a rising edge or positive edge.
14
Q
Negative Edge:
A
A transition from 1 to 0 is a falling edge or negative edge.
15
Q
First Pulse to occur:
A
The first edge of a pulse to occur in time is its leading edge and the last edge to occur is its trailing edge.
16
Q
Leading edge of a positive pulse:
A
For a positive pulse, the leading edge is a 0 to 1 transition and the trailing edge is a 1 to 0 transition.
17
Q
What’s a clock signal?
A
A clock signal is a train (sequence) of pulses used as a timing signal.
18
Q
What can a clock signal controls in a synchronous sequential system?
A
In a fully synchronous sequential system, a single clock signal controls when all the memory elements can change state.
19
Q
Periodic signal:
4
A
- clock signal is periodic.
- time between corresponding edges of a periodic signal is constant.
- changes of state occur at regular intervals.
- period, clock cycle, frequency, clock width, duty cycle measurement.
20
Q
Nonperiodic signal:
A
- the time between corresponding edges of a nonperiodic clock signal is not constant.
- a nonperiodic signal’s clock width may also vary.
21
Q
The clock pulse of a:
- Periodic signal.
- Nonperiodic signal.
A
Refer to the final folder inside the FPGA file.
22
Q
Primary difference between latches and flip-flop:
A
- A latch’s state can be changed by its synchronous inputs during the entire time its clock is asserted.
- A flip-flop’s state can be changed by its synchronous inputs only at the edge of a clock pulse.
23
Q
Which memory element is the most used between latches and flip-flops?
A
Flip-flops are used much more extensively as memory elements in PLD based designs than are latches.
24
Q
Clocked latch/ Gated latch:
8
A
- sensitive to its clock’s level.
- displays a level-sensitive synchronous behavior.
- the state of the latch can be changed by the values of its synchronous inputs during the entire time the clock is at its asserted level.
- The state of the latch at the time its clock changes to its unasserted level is stored in the latch.
- If a latch is sensitive to a high or positive clock level, its clock signal is considered asserted when it is 1.
- If a latch is sensitive to the low or negative clock level, its clock signal is considered asserted when it is 0.
- The value Qt is the previously stored value of Q. That is, the value of Q when CLK was previously changed to its unasserted level.
- When a latch’s clock is at its unasserted logic level, its synchronous inputs have no effect on its state.
25
Function table for a positive-level D latch:
Refer to the final folder inside the FPGA file.
26
Flip-flop:
| 6
1. a memory element whose output can change only at the time of its clock’s transition (edge).
2. has a transition-sensitive synchronous behavior.
3. If a flip-flop is sensitive to a 0-to-1 transition of its clock (rising edge), the flip-flop is said to be positive edge triggered.
4. If a flip-flop is sensitive to a 1-to-0 transition of its clock (falling edge), the flip-flop is said to be negative edge triggered.
5. Whichever edge of its clock a flip-flop is sensitive to is called its triggering edge or active edge.
6. Therefore, a flip-flop’s output can change only once during a clock cycle, at the triggering edge of its clock.
27
Positive edge triggered flip-flop:
If a flip-flop is sensitive to a 0-to-1 transition of its clock (rising edge), the flip-flop is said to be positive edge triggered.
28
Negative edge triggered flip-flop:
If a flip-flop is sensitive to a 1-to-0 transition of its clock (falling edge), the flip-flop is said to be negative edge triggered.
29
Function table for a positive-edge-triggered D flip-flop:
Refer to the final folder inside the FPGA file.
30
Asynchronous inputs:
1. Asynchronous inputs affect a memory element’s state independently of its clock or its synchronous inputs.
2. When power is first applied to a memory element, its initial state is unpredictable.
3. Asynchronous inputs are used to force a memory element into a desired initial state at power on.
4. It is considered bad design practice to use asynchronous inputs to change the state of a memory element subsequent to power on.
5. That is, during normal system operation.
31
D Latch:
| 9
1. A latch’s clock input is often called an enable
input, and labeled EN, G, or LE (latch enable).
2. The input data is said to “flow through” to the output, and the latch is termed transparent.
3. Such a latch may also be referred to as a transparent high latch.
4. When CLK is changed from 1 to 0, Q keeps the value it had at the time CLK was last equal to 1.
5. Under this clock condition, the value of D when CLK was last a 1 is stored.
6. As long as CLK remains 0, any subsequent changes in D have no effect on Q.
7. Since changes in Q, corresponding to changes in D, are conditioned on the clock level, D is a synchronous input.
8. Since the value stored in a positive-level D latch is always equal to the value of D when CLK was last equal to 1, the D input is thought of as the data input.
9. A D latch may also have a Q bar output, which is, by definition, the complement of Q.
32
D latch module (diagram):
(a) positive-triggered edge
(b) negative-triggered edge
Refer to the final folder inside the FPGA file.
33
Latch inference:
| 7
1. When a latch must be synthesized is called latch inference.
2. Cause a memory element to be synthesized by writing code that is recognized as implying the need for a memory element.
3. Latch is inferred when a statement conditionally makes an assignment to a signal or variable and the condition does not involve
a clock edge.
4. Such an assignment is called an asynchronous assignment.
5. If statement whose if clause contains an asynchronous assignment to a signal, but which has no terminating else clause, causes a synthesizer to infer that a latch is required.
6. A latch is required because, when the condition is not true, the signal is not assigned a new value.
7. Therefore, the signal must retain its previous value, necessitating a latch.
34
Template for latch inference using an if statement:
Refer to the final folder inside the FPGA file.
35
D latch description:
| 4
1. The order of the clock and the other inputs in the sensitivity list is not important.
2. However, the sensitivity list must contain all of the signals read within the process.
3. Since there is no else clause, if clk is not '1', there is no assignment to q. This later condition implies that the old value of q must be remembered, and hence the need for a latch.
4. Since we intended to describe a D latch, the else clause was intentionally left out so that the synthesizer infers the need for a latch.
5. D latch description can be written so that combinational logic is synthesized prior to the latch’s D input.
6. The inner if statement is complete and is synthesized to a multiplexer. The outer if statement is incomplete, causing the
multiplexer’s output to be latched.
7. A latch may also have an asynchronous set input, an asynchronous clear input, or both. These inputs are used, independently of the clock level, to force Q to be a 1 or a 0. The term preset is synonymous with set and the term reset is synonymous with clear.
8. Any asynchronous inputs must be kept unasserted for normal synchronous operation.
36
Detecting clock edges:
Flip-flop is only sensitive to its synchronous inputs at the occurrence of a triggering clock edge, its description requires detection of each triggering clock edge.
37
Expression of a positive clock-edge condition:
1. clock_signal_name'event and clock_signal_name = '1'
2. not clock_signal_name'stable and clock_signal_name = '1'
3. rising_edge(clock_signal_name)
38
Expression of a negative clock-edge condition:
1. clock_signal_name'event and clock_signal_name = '0'
2. not clock_signal_name'stable and clock_signal_name = '0'
3. falling_edge(clock_signal_name)
39
D Flip-Flops:
| 7
1. A D flip-flop is an edge-triggered memory element that transfers the value on its D input to its Q output when a triggering edge occurs at its clock input.
2. This output value is stored until the next
triggering clock edge.
3. Thus, a D flip-flop can change its state only once during a clock cycle.
4. Synchronous inputs to a flip-flop are sampled only at a triggering clock edge.
5. Thus, the flip-flop’s output can change value in response to synchronous inputs only at a triggering clock edge.
6. A VHDL statement causes a synchronous assignment when a signal or variable is updated as a direct result of a clock edge condition evaluating true.
7. During synthesis, a signal or variable updated by a synchronous assignment results in a flip-flop being inferred.
40
D Flip-Flops (diagram):
(a) positive-triggered
(b) negative-triggered
Refer to the final folder inside the FPGA file.
41
Enabled (Gated) Flip-Flop:
((All previous D flip-flop examples stored the data at their D inputs at each triggering clock edge. Thus, data was stored for no longer than one clock cycle. Often there is a need to have a flip-flop store its data for more than one clock cycle))
1. Often there is a need to have a flip-flop store its data for more than one clock cycle.
2. This is achieved by having the flip-flop store its input data only at selected triggering clock edges and not at others.
3. At the other triggering clock edges, we want the flip-flop to remain in its previous state.
4. To accomplish this, we add an enable (gate) input to the flip-flop.
5. A D flip-flop with an enable input stores its input data at a triggering clock edge only if its enable input is asserted.
42
Other Flip-Flops:
1. There are four basic types of flip-flops that have traditionally been used in digital systems: D, S-R, J-K, and T. These flip-flops differ primarily in the number and function of their synchronous inputs.
((2. In the traditional design of finite state machines (FSMs), where typically only a few flip-flops were provided in each IC package (using small-scale integration), the use of S-R, J-K, or T flip-flops instead of D flip-flops often allowed simplification of the combinational logic required to drive the flip-flops’ inputs.))
((3. This would typically result in the reduction of the number of IC packages required to implement the system.))
43
Flip-flop characteristic equations:
Refer to the final folder inside the FPGA file.
