comp arch Flashcards
(34 cards)
advantage and disadvantage of more data type
benefit is code is smaller and faster or more optimised.
disadvantage is this is more work for the microarchitect
advantages and disadvantages of complex instructions and data types
advantage: denser encoding -> smaller code size -> better memory footprint of instructions, saves off chip bandwidth, fewer cache misses
simpler compiler
disadvantages compiler has less opportunity to optimize. larger chunks of work. more complex hardware
what is the 5 stage pipeline
IF ID EX MEM WB
what isa does apple ues?
ARM except for on the watch OS
data path and control path in multi cycle and single cycle machines?
single cycle:
control signal are generated in the same clock cycle as the one during which the data signals are operated on.
everything related to an instruction happens in one clock cycle
multi cycle:
control cycles needed in the next cycle can be generated in the current cycle
latency of control processing can be overlapped with latency of datapath operation (more parallelism)
advantages and disadvantages of a multi clock cycle design
advanatges:
*higher clock freq as we are only limited by time of longest step in a stage
*simpler instructions take only a few clock cycles
* we can reuse expensive hardware across multiple cycles
disadv:
* hardware overhead for storing intermediate results in registers
*sequential logic overhead paid many times for each instruction
what is the motivation to go from single cycle to multi cycle?
- In a single-cycle processor, each instruction must complete within one cycle, which typically requires making the cycle long enough to accommodate the slowest instruction.
- resources can be shared. like ALU for address addition and ALU for add operation
- complex instructions possible as they don’t limit simple instructions
- Cycle Time Reduction: Multi-cycle processors break down the execution of an instruction into several shorter steps, each completing in one cycle.
what are causes of pipeline stalls?
data dependence
control dependence
resource dependence/contention
how to handle resource contention?
duplicate the resources.
detect the pipeline stages that want resources and give to the one ahead so that the pipeline can keep moving
What optim can you do since reg operations are fast
since register operations are super fast you can do operation in front of the pipeline in the first half and do the operation behind in the second half
what are the types of data dependence
- flow dependence: a consumer instruction is reading a data a prior instruction has written to (ReadAfterWrite dependency)
r3<-r1 or r2
r5<- r3 or r4
This is a true dependence as there is data flow - Anti dependence : Write after read dependence (WAR). not a true dependence
r3<- r1 op r2
r1 <- r4 op r5 - output dependence: Write after Write (WAW dependence)
r3<- r1 op r2
— r5 <- r3 op r4
r3 <- r6 op r7
what is interlocking?
detection of dependence between instructions in a pipelined processor to guarantee correct execution
you can do interlocking in software or hardware
MIPS - microprocessor without interlocking pipeline stages.
what is scoreboarding?
Scoreboarding:
Each register in register file has a valid bit associated with it.
An instruction that is writing to the register resets the valid bit
an instruction in the decode stage checks if its source and destination registers are valid
what are approaches to dependence detection?
scoreboarding and conbinational dependence check logic
what is combinational dependence check logic?
you compare at decode stage if the register you’re going to read or write is being written to by any of the stages ahead using comparator and then stall if there is a dependence
what is data forwarding?
if a value an instruction needs is not ready because it hasn’t been written by an incomplete instruction in the pipeline but it has been computed then it can be forwarded directly without waiting for writing into registers
Reasons for pipeline stalls
Resource contention
Data/ Control dependence
Long latency operations
when might it be difficult to do data forwarding?
if you have to forward data from MEM stage which is often the bottleneck this might increase cycle time and so you might not want to do that
what is control dependence?
when you have branch or conditional jump and stuff you don’t know what the pc is for next instruction so you would have to stall
how do you resolve control dependence?
branch prediction
variable length execution due to multiplication with what inputs? what does this means about hardware vs software optimizations
if you’re multiplying by 0 you could be done super fast and only hardware knows this during runtime and can process this to benefit
what is fine grained multithreading
you overlap stages from multiple threads to get faster processing as you can now get more flexibiility with stalls
how does multi cycle execution stages affect pipelining
it results in wb for all instructions after the multistage execute to stall till multistage execute is complete
how do you solve multicycle execute causing issues in pipelining?
you use
