Computer Architecture Flashcards
(21 cards)
Explain the Von Neumann architecture.
Components: CPU (ALU + Control Unit), Memory, I/O devices, Bus.
Stored-program concept: instructions and data share memory.
Von Neumann bottleneck: data/instruction compete for bandwidth.
What is cache memory and cache hierarchy?
Cache stores frequently used data close to CPU.
L1: Fastest, smallest, per-core
L2: Larger, slower, may be shared
L3: Largest, shared by cores
Policies: LRU, LFU, Random.
Explain instruction pipelining.
Pipeline stages: Fetch, Decode, Execute, Memory, Write-back.
Hazards: Structural, Data, Control.
Handled by techniques like forwarding and branch prediction.
Describe the Von Neumann architecture and the stored program concept.
Von Neumann Architecture: A design model where:
- Both program instructions and data are stored in the same memory (RAM).
- A single shared bus is used for fetching both instructions and data.
Stored Program Concept: The fundamental principle that programs (instructions) are treated as data and can be stored in memory, allowing them to be easily changed and manipulated.
What are the roles of the CPU, Memory, I/O systems, and Buses?
CPU (Central Processing Unit): The ‘brain’ that executes instructions from programs.
Memory (RAM): Volatile storage for currently executing programs and their data.
I/O Systems: Devices that allow the computer to interact with the outside world (e.g., keyboard, mouse, disk drives).
Buses: Communication channels that transfer data and signals between computer components (e.g., data bus, address bus, control bus).
How does Two’s Complement represent signed integers, and what are its advantages?
Representation: For an N-bit number, a positive number is its standard binary representation. A negative number is found by inverting all the bits of its positive counterpart and adding 1.
Advantages:
- There is only one representation for zero (unlike sign-magnitude).
- Standard addition and subtraction operations work for both signed and unsigned numbers without special logic.
Explain the components of the IEEE 754 floating-point standard.
A standard for representing floating-point (real) numbers.
Components of a 32-bit number:
1. Sign Bit (1 bit): 0 for positive, 1 for negative.
2. Exponent (8 bits): Represents the magnitude of the number in a biased format.
3. Mantissa/Fraction (23 bits): Represents the significant digits of the number (the fractional part).
What are the main types of instructions in an ISA?
Arithmetic Instructions: Perform math operations (e.g., ADD, SUB, MUL).
Logical Instructions: Perform bitwise operations (e.g., AND, OR, NOT).
Memory Access Instructions: Move data between registers and memory (e.g., LOAD, STORE).
Control Flow Instructions: Change the program execution sequence (e.g., JUMP, BRANCH).
What are addressing modes? Explain Immediate and Direct modes.
Addressing Modes: The methods used by an instruction to specify the location of its operand(s).
Immediate Mode: The operand is a constant value contained within the instruction itself.
Direct Mode: The instruction contains the memory address where the operand is stored.
Describe the Fetch-Decode-Execute cycle.
The fundamental operational cycle of a computer.
1. Fetch: Retrieve the next instruction from memory (at the address in the Program Counter).
2. Decode: The Control Unit interprets the instruction to determine what action to perform.
3. Execute: The instruction is carried out. This may involve the ALU, memory access, or register transfers.
Compare a hardwired vs. a microprogrammed Control Unit.
Hardwired Control Unit:
- Implemented as a finite state machine using digital logic circuits.
- Fast and efficient for a given instruction set.
- Inflexible; difficult to modify or add new instructions.
- Common in RISC processors.
Microprogrammed Control Unit:
- Instructions are interpreted by a microprogram (a sequence of micro-instructions) stored in a special memory (control store).
- More flexible; easy to add/change instructions by updating the microprogram.
- Slower due to the extra memory access step.
- Common in CISC processors.
Explain data hazards and how ‘forwarding’ resolves them.
Data Hazard: Occurs when an instruction depends on the result of a previous instruction that is still in the pipeline and not yet complete.
- Example: RAW (Read After Write) hazard.
Forwarding (or Bypassing): A technique where the result from an ALU operation is sent directly to the input of another ALU for a subsequent instruction, bypassing the need to wait for the result to be written back to a register. This resolves many data hazards without stalling the pipeline.
What are control hazards and how does branch prediction work?
Control Hazard: Occurs when the pipeline doesn’t know which instruction to fetch next because of a branch instruction. This forces the pipeline to stall until the branch outcome is known.
Branch Prediction: A technique where the CPU predicts the outcome of a branch and speculatively fetches instructions from the predicted path. If the prediction is correct, no time is lost. If it’s incorrect, the pipeline is ‘flushed’ (incorrect instructions are discarded) and the correct path is taken, incurring a penalty.
Explain cache replacement policies like LRU and FIFO.
When a cache is full and a new block needs to be loaded, a replacement policy decides which existing block to evict.
LRU (Least Recently Used): Evicts the block that has been accessed least recently. Generally performs well but is complex to implement perfectly.
FIFO (First-In, First-Out): Evicts the block that has been in the cache the longest, regardless of how often it was accessed.
Compare write-through and write-back cache policies.
Write-Through:
- When the CPU writes to the cache, the data is written to both the cache and main memory simultaneously.
- Simpler to implement and ensures memory is always up-to-date.
- Can be slow due to the high volume of memory traffic.
Write-Back:
- The CPU only writes to the cache line. The line is marked as ‘dirty’.
- The modified line is only written back to main memory when it is evicted from the cache.
- Faster and reduces memory traffic, but more complex to implement.
How do you calculate CPU time using CPI, instruction count, and clock rate?
CPU Time = Instruction Count * CPI * Clock Cycle Time
Or, CPU Time = (Instruction Count * CPI) / Clock Rate
Instruction Count: The total number of instructions executed by a program.
CPI (Cycles Per Instruction): The average number of clock cycles required per instruction.
Clock Rate: The number of clock cycles per second (in Hz).
What is Amdahl’s Law?
A formula used to find the maximum theoretical speedup of a system when only a part of it is improved.
Core Idea: The speedup is limited by the fraction of the task that cannot be parallelized or improved. For example, if 90% of a program can be made faster, the overall speedup is limited by the 10% that remains unchanged.
Explain the role of the stack and system calls in assembly programming.
Stack: A region of memory used for temporary data storage, organized in a Last-In, First-Out (LIFO) manner.
- Used for storing local variables, passing parameters to functions, and saving return addresses during procedure calls.
System Call: A request from a user-level program to the operating system for a service that requires kernel-level privileges (e.g., reading a file, printing to the console).
Compare interrupt-driven I/O with polling.
Polling: The CPU repeatedly checks the status of an I/O device to see if it’s ready for a data transfer. This is simple but wastes CPU cycles.
Interrupt-driven I/O: The I/O device sends a signal (an interrupt) to the CPU when it’s ready. The CPU then suspends its current task, services the I/O device, and then resumes. This is much more efficient as the CPU can do other work while waiting.
How does Direct Memory Access (DMA) work?
DMA is a feature that allows I/O devices to transfer data directly to or from main memory without involving the CPU.
Process:
1. The CPU programs a DMA controller with the source/destination addresses and data count.
2. The DMA controller handles the entire data transfer.
3. The DMA controller sends an interrupt to the CPU only when the transfer is complete.
Benefit: Frees the CPU from the burden of byte-by-byte data transfer.
What is the purpose of a cache coherence protocol like MESI?
Purpose: To maintain consistency of data stored in the local caches of multiple processors.
Problem: If one processor updates a value in its cache, other caches holding the same data become stale.
MESI Protocol: An invalidation-based protocol where each cache line is marked with one of four states (Modified, Exclusive, Shared, Invalid) to track its status and ensure all processors see the correct, most recent data.
