computer architecture pt2

Question 1

FDE cycle

Answer 1

CPU sends value of PC to be copied to MAR
PC increments
get instruction identified by MAR and copy into MDR
move instruction from MDR to IR
move instruction from IR to CU for decoding:
-sends operation to ALU
-put address of data to be operated on in a register
-send address of data from register to MAR
-read data and place in MDR
-move data from MDR to an accumulator in the ALU
-complete operation and store result in an accumulator in the ALU

Question 2

uses of alternative addressing modes

Answer 2

• addressing large amount of memory with few bits
• use indexes to loop or examine a table or array
• address registers (bc faster than addressing memory)
• relocate data or programs in memory

Question 3

direct addressing

Answer 3

the address used is the address holding the data to be operated on

Question 4

immediate addressing

Answer 4

the address read in the instruction is the data to be used (e.g. for constants like 1)

Question 5

indirect addressing *

Answer 5

the address used is the address of the memory location holding the address of the data item to be operated on

Question 6

register indirect addressing

Answer 6

the address read in the instruction is the address of the register holding the data item to be operated on

Question 7

indexed addressing @

Answer 7

the address in the instruction has an index (stored in a register) which is added to obtain the address of the data

Question 8

impure code

Answer 8

when instructions are changed during execution

changed instructions have to be reset before being run again else program will run differently

Question 9

full instruction structure

Answer 9

opcode + addressing mode + address 1 + address 2

Question 10

absolute addressing

Answer 10

the address read is the address that should be gone to

Question 11

relative addressing

Answer 11

the address read in the instruction is an offset to the current instruction address (i.e. program counter value)

Question 12

base offset addressing

Answer 12

the address read in the instruction is offset by the current value in a special base register

Question 13

type of instructions

Answer 13

Single operand manipulation: negating, inc/decrementing, setting reg = 0
Arithmetic: floating point, add/sub/div/multiplication
Program control: branching, call, jumps, return
Boolean logic: shift/rotate, bit manipulation- allowing the design of own flags so controlling program flow. inc set/test instructions
Data movement: between registers, reg+memory + memory locations
Stack: pop/push in a LIFO structure
Multiple data, single instruction: multimedia- single instruction on a large amount of date e.g. pixels

Question 14

MIPS principles

Answer 14

1. simplicity favours regularity
2. makes the common case faster
3. smaller is faster
4. good design demands good compromises

Question 15

1.simplicity favours regularity

Answer 15

consistent instruction format with same number of operands- 2 sources + 1 destination- : easier to encode + handle in hardware

Question 16

2. makes common case faster

Answer 16

only includes simple, commonly used instructions
for complex operations, use more instructions
results in simpler, smaller, faster hardware
(RISC)

Question 17

3. smaller is faster

Answer 17

few registers used

Question 18

4. good design demands good compromises

Answer 18

more instruction formats = more flexibility
number of instruction formats kept small to adhere to principle 1 + 3
other formats may appear in assembler but transformed in machine code to fit format

Question 19

3 instruction formats

Answer 19

• R type: register operands
• I type: immediate operand
• J type: jumping

Question 20

r-type instruction formats

Answer 20

opcode (6 bits, 0 for r-type), rs, rt (source registers, 5 bits), rd (destination register, 5 bits), shamt (shift amount, 5 bits, 0 if not shift operation), func (function, operation to be done, 6 bits)

Question 21

register field values: shift bits in register 17 left 5 places and put in in register 16

Answer 21

opcode = 0
rs = 0
rt = 17
rd = 16
shamt = 5
func = 0

Question 22

i-type instruction formats

Answer 22

opcode (6 bits), rs, rt (source registers, 5 bits), imm (16 bit twos complement immediate)
rt is used as a destination for some instructions e.g. addi

Question 23

addi $s0, $s1, 5

Answer 23

(immediate type) add the value in register 17, and the number 5, and place in register 16

Question 24

lw $t2, 32($0)

Answer 24

load word at address 32+ contents of register 0, and store in register 10

Question 25

sw $s1, 4($t1)

Answer 25

store word in register 17 at address 4+ contents of register 9

Question 26

li $s0, 5 | aka ori $s0, $0, 5

Answer 26

(immediate type) load immediate 5 and store in register 16 | in machine code, swap round $0 and $s0

Question 27

j-type

Answer 27

6 bit opcode, 26 bit address | typically use r type rather than this in assembler: jr name/ jr $0 i.e. jump to name or address contained in register

Question 28

types of addressing the operands

Answer 28

register only: add $s0, $s1, $s2 immediate: addi $s0, $s1, 5 (5+ contents of s1, store in s0: s1 = rs, s0 = rt) base address: address of operand = base address + signed immediate e.g. lw $1, 0($2) PC-relative (jump so far from current position): beq $t0, $0, 3 (offset of 3 from PC value if first two values are equal)

Question 29

loading 32 bit words with only 16 bit intermediates

Answer 29

first load first half then add on the second half lui $0, 0xFEDC ori $s0, $s0, 0x8765

Question 30

how to make OS calls

Answer 30

use register $v0, system call depends on contents of $v0. assembly code 'syscall'

Question 31

multiplication MIPS

Answer 31

mul: 32 bit result, no overflow checking mult: 32 bits multiplied resulting in 64 bit result (mult $s0, $s1) stored in special reg: lo/hi turn mult in to mul $v2,$s3,$t0 by mflo $v2

Question 32

division MIPS

Answer 32

div $s0, $s1 quotient in lo remainder in hi

Question 33

move from lo/hi special registers

Answer 33

mflo $s2 | mfhi $s2

Question 34

MIPS: jal instructions

Answer 34

jump and link: e.g. jal adder, jumps to portion labeled "adder:", and puts return address (current address) in $ra return back justing jr $ra

Question 35

caller vs callee

Answer 35

caller: passes arguments to callee using $a0 - $a4 and jumps to callee using jal callee: performs function + returns result using $v0-$v1, returns to point of call using jr $ra, shouldnt overwrite registers needed by caller e.g. $s0-$s7, $ra, $sp- if using the registers, values kept on stack

Question 36

stack

Answer 36

dynamically sized chunk of memory with $sp containing address of head of stack

Question 37

pushing to stack

Answer 37

move stack pointer down one position and write value addi $sp, $sp, -4 sw $s0, 0($sp)

Question 38

popping from stack

Answer 38

read and move pointer back up four places addi $sp, $sp, 4 lw $s0, 0($sp)

Question 39

$ra when calling recursive procedures

Answer 39

push value of $ra onto stack before calling a function so can reinstate afterwards

Question 40

conventional orders of caller

Answer 40

- arguments in $a0-$a3 - save any needed registers: $ra, maybe $t0-$t9 - jal callee - restore registers - check $v0 for result

Question 41

conventional orders of callee

Answer 41

- save registers that may be disturbed $s0-$s7 - perform function - result in $v0 - restore registers - jr $ra

Question 42

architecture

Answer 42

consists of the instruction set + implies an architectural state: - value of PC - state of all architecture defined registers

Question 43

microarchitecture

Answer 43

how to implement an architecture in hardware. consists of: - datapath: functional blocks and registers - control: control signals

Question 44

MIPS

Answer 44

- approx 80 instructions - 32 general purpose instructions $0- $31 - super pipelined: each instruction is broken down into a sequence of 'micro' instructions - RISC - $0 is special and always contains 0

Question 45

program counter

Answer 45

32 bit register: PC' = input = address of next instruction, output PC = points to current instruction

Question 46

instruction memory

Answer 46

one read port | read port: 1 read address, A, of 32 bit length, reads 32 bit data (instruction) and place on RD

Question 47

register file

Answer 47

one read port one write port. read port: 2 input addresses of 5 bits (addressing one of 32 registers). addresses read from these are placed on RD1 and RD2 outputs write port: CLK, WD- 32 bit data to be written, A3 5 bit destination address, WE- write enable: if 1 then written to specified register on a rising edge of clock

Question 48

data memory

Answer 48

one read port one write port read port: 32 bit address, A write port: 32 bit write data, WD WE: write enable, if 1 WD written into address A on rising edge else data read from A and placed on RD output (32 bit)

Question 49

all reads in MIPS state elements are 'combinational'

Answer 49

change in address results in change in read data (after a delay). writes are only on a rising clock edge

Question 50

further registers

Answer 50

32 in 'floating point unit': each hold a single precision floating point value. pairs store double precision numbers mul.s $f0, $f1, $f2 multiply f2 and f1 and store in f0 mul.d operands are doubles stored in $f2,$f3 and $f4,$f5, result is stored in $f0 and $f1. also exception and interrupt handling registers

Question 51

mtc1 $s0, $f0 | mfc1 $f0, $s0

Answer 51

move between CPU and FPU move to coprocessor 1 move from coprocessor 1

Question 52

lwc1 $f0, 4($s0) | swc1 $f0, 4($s0)

Answer 52

load word save word | memory address is in CPU

Question 53

l. d $f0, 4($s0) | s. d $f0, 4($s0)

Answer 53

load double and save double precision numbers

Question 54

casting: | cvt.s.w $f0,$f0

Answer 54

converts from int (w) to single FP

Question 55

Single precision (32-bit) floating point numbers have

Answer 55

1 sign bit 8 bit exponent 23 bit mantissa

Question 56

casting errors

Answer 56

if number needs more digits for mantissa and only 23 provided

Question 57

floating point branches: Logical comparisons

Answer 57

``` equality: c.eq.s, c.eq.d Less than: c.lt.s, c.lt.d Less than or equal: c.le.s, c.le.d (ge = greater than or equal) result of logical comparison stored in fpcond ```

Question 58

fp branches: conditional branch

Answer 58

bclf: branches if fpcond is FALSE bclt: branches if fpcond is TRUE

Question 59

MMIO

Answer 59

memory mapped input output: devices connected to same address bus as main memory and are each allocated address space (input devices read like any other memory, output devices written to like any other memory). CPU doesn't see difference between IO and memory

Question 60

port-mapped IO

Answer 60

have a separate address space for IO and use special IO instructions to access IO

Question 61

MARS: keyboard allocated 2 memory addresses

Answer 61

0xffff0000 control: bit 0 = ready bit, 1 if unread input from keyboard bit 1 = interrupt bit, if 1 then keyboard triggers an interrupt 0xffff0004 data: contains the ASCII code of the last key pressed. on read it triggers the ready bit to be reset

Question 62

MARS: display output

Answer 62

0xffff0008 control: bit 0 = ready bit, 1 if display is ready to take another input bit 1 = interrupt bit, if 1 then display ready triggers an interrupt 0xffff000c data: set with the ASCII code of the character on write: triggers the ready bit to be reset

Question 63

exception

Answer 63

anything that happens that triggers an unscheduled function call in the middle of a user program. caused by hardware = interrupt, software = traps e.g. undefined function

Question 64

when an exception occurs

Answer 64

program records cause of exception, jumps to exception handler and returns to program

Question 65

special addresses used when exception occurs

Answer 65

EPC: stores value of program counter status: records whether user or kernel code was being executed cause: records cause of exception BadVaddress: stores the bad address that caused an exception -these are stored in coprocessor 0 mfc0 $t0 EPC- moves contents of EPC to t0

Question 66

flow during exception

Answer 66

processor stores cause and exception PC in cause and EPC processor jumps to exception handler exception handler: saves register on stack reads cause from cause register mfc0 $t0, Cause handles exception restores registers returns to program mfc0 $k0, EPC jr $k0 -must save all registers so registers can be reinstated and program run as if nothing had happened