Computer Organization and Architecture Flashcards

(111 cards)

1
Q

What is the file format of a file with the signature “{\rtf”

A

.rtf (Rich Text Format)

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2
Q

What is the file format of a file with the signature “ID3”

A

.mp3 (MPEG Audio Layer-3)

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3
Q

What is the file format of a file with the signature “RIFF”

A

.wav (Wave)

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4
Q

What is the file format of a file with the signature “BM”

A

.bmp (Bitmap Image)

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5
Q

What is the file format of a file with the signature “……JFIF”

A

.jpeg (Joint Photographic Experts Group)

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6
Q

What is the file format of a file with the signature “ID3”

A

.mpeg (Moving Picture Experts Group)
AND
.mp3 (MPEG Audio Layer-3)

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7
Q

What is the file format of a file with the signature “MZ”

A

.exe (Executable File Format)

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8
Q

What is the file format of a file with the signature “.ELF”

A

.elf (Executable and Linkable Format)

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9
Q

What is the file format of a file with the signature “…”

A

.gz (GZIP)

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10
Q

What is the file format of a file with the signature “PK”

A

.zip (ZIP)

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11
Q

What are file format signatures written in?

A

Hexadecimal

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12
Q

What is the Prefix and Symbol for Quintillion?

A

Exa (E)

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13
Q

What is the Prefix and Symbol for Quadrillion?

A

Peta (P)

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14
Q

What is the Prefix and Symbol for Trillion?

A

Tera (T)

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15
Q

What is the Prefix and Symbol for Billion?

A

Giga (G)

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16
Q

What is the Prefix and Symbol for Million?

A

Mega (M)

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17
Q

What is the Prefix and Symbol for Thousand?

A

Kilo (K)

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18
Q

What is the Prefix and Symbol for Thousandth?

A

milli (m)

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19
Q

What is the Prefix and Symbol for Millionth?

A

micro (μ)

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20
Q

What is the Prefix and Symbol for Billionth?

A

nano (n)

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21
Q

What is the Prefix and Symbol for Trillionth?

A

pico (p)

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22
Q

What is the Prefix and Symbol for Quadrillionth?

A

femto (f)

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23
Q

What is the Prefix and Symbol for Quintillionth?

A

atto (a)

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24
Q

Time and frequency have a base of 10 and the exponent increases by intervals of ___?

A

3

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25
Data Storage has a base of 2 and the exponent increases by intervals of __?
10
26
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for Halt (HLT)?
000
27
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for ADD?
1XX
28
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for SUBTRACT? (SUB)
2XX
29
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for STORE? (STA)
3XX
30
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for LOAD? (LDA)
5XX
31
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for BRANCH UNCONDITIONAL? (BRA)
6XX
32
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for BRANCH ON ZERO? (BRZ)
7XX
33
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for BRANCH ON POSITIVE? (BRP)
8XX
34
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for INPUT? (INP)
901
35
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for OUTPUT? (OUT)
902
36
For the LMC what is the 1 Digit Opcode and 2 Digit Operand for DATA?
there isn't one
37
What F-D-E Instruction is being described here and what is the code? PC -> MAR MDR -> IR
000, HLT
38
What F-D-E Instruction is being described here and what is the code? ``` PC -> MAR MDR -> IR IR[ADDR] -> MAR A + MDR -> A PC + 1 -> PC ```
1XX, ADD
39
What F-D-E Instruction is being described here and what is the code? ``` PC -> MAR MDR -> IR IR[ADDR] -> MAR A - MDR -> A PC + 1 -> PC ```
2XX, SUB
40
What F-D-E Instruction is being described here and what is the code? ``` PC -> MAR MDR -> IR IR[ADDR] -> MAR A -> MDR PC + 1 -> PC ```
3XX, STA
41
What F-D-E Instruction is being described here and what is the code? ``` PC -> MAR MDR -> IR IR[ADDR] -> MAR MDR -> A PC + 1 -> PC ```
5XX, LDA
42
What F-D-E Instruction is being described here and what is the code? PC -> MAR MDR -> IR IR[ADDR] -> PC
6XX, BRA
43
What F-D-E Instruction is being described here and what is the code? ``` PC -> MAR MDR -> IR IF A == 0 THEN IR[ADDR] -> PC ELSE PC + 1 -> PC ```
7XX, BRZ
44
What F-D-E Instruction is being described here and what is the code? ``` PC -> MAR MDR -> IR IF A >= 0 THEN IR[ADDR] -> PC ELSE PC + 1 -> PC ```
8XX, BRP
45
What F-D-E Instruction is being described here and what is the code? PC -> MAR MDR -> IR INBOX -> A PC + 1 -> PC
901, INP
46
What F-D-E Instruction is being described here and what is the code? PC -> MAR MDR -> IR A -> OUTBOX PC + 1 -> PC
902, OUT
47
The architecture concept that underlies the Von Neumann and Harvard architectures
Stored-Program Concept
48
A register that can be directly accessed by the programmer for any purpose
General-Purpose Register
49
An expression composed of Boolean variables and logical connectives
Boolean Expression
50
The numeric value that represents an instruction to the CPU
Opcode
51
The part of the CPU that manages data passed to or fetched from memory
Memory Management Unit (MMU)
52
The vocabulary of commands understood by the CPU
Instruction set architecture
53
The part of the CPU that performs the fetch and decode steps of an assembly instruction
Control Unit (CU)
54
The part of the CPU that performs arithmetic and logic operations
Arithmetic Logic Unit (ALU)
55
The process used by the CPU to retrieve, interpret, and perform each instruction of a program
Fetch-Decode-Execute (F-D-E)
56
ARM _______ dictate which instructions and architectural features are available to a process.
modes of operation
57
Which ARM privilege level allows the FEWEST number of features of the architecture to be available to a process?
PL0
58
ARM uses _____ to move data from register-to-register, register-to-memory, and memory-to-register.
data movement instructions
59
The _____ is a last-in-first-out memory structure used by ARM for short term storage of information by the CPU.
stack
60
A _____ in ARM, is a block of code labeled for reuse.
subroutine
61
ARM _____ instructions perform logical operations on 0s and 1s.
Boolean Logic
62
What are the ARM Modes of Operation?
User (usr) - User mode is the default ARM program execution state and is used for executing most application programs System (sys) - Runs privileged OS tasks (routine OS business) FIQ - Used when handling high priority (fast) interrupts IRQ - Used when handling low priority (normal) interrupts Supervisor (svc) - Protected mode for the OS (system calls) Abort - Used to handle memory access violations Undef - Used to handle undefined or unimplemented instructions Secure Monitor (mon) - Used to transfer control from non-secure to secure and vice versa by the processor.
63
ARM _____ instructions operate on integers and floating-point numbers.
Arithmetic
64
ARM _____ are hardware enforced permissions to ensure system security through process isolation.
Privilege levels
65
In ARM, _____ defines where to find the data (operand) to be manipulated by the instruction (opcode).
Operand Addressing Mode
66
ARM _____ instructions use branching to change the order in which the program executes.
flow control
67
What are the ARM control and status registers?
``` Program Counter (control) CPSR (Current Program Status Register) (status) ```
68
The _____ registers hold information about the most recently performed ALU operation, memory alignment, endianess, enabling and disabling of interrupts, and set processor-operating mode.
control and status
69
The _____ register points to the next instruction in memory.
Program Counter (PC)
70
The _____ stores the return address for subroutines.
Link Register (LR)
71
_____ registers can be directly accessed by the programmer for any purpose.
General-Purpose
72
_____ registers are used for base locations for program instructions, data, and the stack.
Segment
73
The _____ points to the top of the stack.
Stack Pointer (SP)
74
The _____ holds the current condition of the program.
Current Program Status Register (CPSR)
75
The Operand Addressing mode of the following instruction is: ldr r0, [r1], #24
Post-Indexed Memory
76
The Operand Addressing mode of the following instruction is: sub r0, r7, r6
Register
77
The Processor Architecture and Operand Addressing mode of the following instruction is: ldr r0, [pc, #8]
ARM/PC-Relative
78
The Operand Addressing mode of the following instruction is: ldr r0, [r1]
Register Indirect Memory
79
The Processor Architecture and Operand Addressing mode of the following instruction is: str r0, [r3]
ARM/Register Indirect Memory
80
The Operand Addressing mode of the following instruction is: str r0, [r1, #8]!
Pre-indexed memory
81
The Operand Addressing mode of the following instruction is: mov r0, #2
ARM/Immediate
82
The Operand Addressing mode of the following instruction is: add r0, #4, #6
Immediate
83
Which registers are general-purpose registers in an ARM processor
r0-r12
84
Which registers are segment registers in an ARM processor (the R number)
r13-r14
85
What is another name for the ARM processor register R13?
Stack pointer (SP)
86
What is another name for the ARM processor register R14?
Link Register (LR)
87
Which register is the control register in an ARM processor
Program Counter (PC)
88
Which register is the status register in an ARM processor
Current program status register (CPSR)
89
Which ARM mode of operation is used to transfer between secure and non-secure?
Secure Monitor (mon)
90
Which ARM mode of operation is used to handle undefined or unimplemented instructions?
Undef
91
Which ARM mode of operation is used to handle memory access violations?
Abort
92
Which ARM mode of operation is used to handle system calls?
Supervisor (svc)
93
Which ARM mode of operation is used to handle low priority interrupts?
IRQ
94
Which ARM mode of operation is used to handle high priority interrupts?
FIQ
95
Which ARM mode of operation is used to handle privileged OS tasks?
System (sys)
96
Which ARM mode of operation is used to handle routine user process execution?
User (usr)
97
Which ARM privilege level is used while executing user processes?
PL0
98
Which ARM privilege level is used while executing a system call?
PL1
99
x86 _____ use branching to change the order in which the program executes.
Flow Control Instructions
100
In x86 _____ defines where to find the data (operand) to be manipulated by the instruction (opcode).
Operand Addressing Mode
101
x86 _____ work on integers and floating point numbers.
Arithmetic Instructions
102
x86 uses _____ to move data from register-to-register, register-to-memory, and memory-to-register.
Data movement instructions
103
in x86 the privilege levels are known as _____ and provide hardware enforced permissions to ensure system security much like ARM architecture.
Protection Rings
104
x86 _____ perform logical operations on 0s and 1s.
Boolean Logic Instructions
105
in x86, which category of registers do the following registers belong to? AX, BX, CX, DX, SI, DI, BP, SP
General Purpose Registers (GPR)
106
The _____ register is used for arithmetic and logical operations.
AX (Accumulator)
107
The _____ points to the next instruction in memory.
IP (Instruction Pointer)
108
Which category of registers do the following registers belong to? IP, FLAGS
Control and Status registers
109
Which category of registers do the following registers belong to? CS, DS, SS, ES, FS, GS
Segment Registers
110
The _____ register is used for string and loop operations.
CX (Counter)
111
The _____ register holds the condition of the program.
FLAGS