Computer System Architecture

Question 1

Define Digital Abstraction

Answer 1

Simplifying the design and analysis of digital circuits by focusing on the discrete values of 0 and 1, rather than then continuous voltage levels.

Question 2

Why not 1024 Registers?

Answer 2

Following are reasons why we don’t have 1024 registers

1. Instruction Encoding become complex
2. Building Cost increases
3. More transistors and interconnects increasing capacitance.
4. Decoding complexity increases.
5. Overall Propagation Delay Increases inturn decreasing performance.
6. Context Switching in OS is another issue - as register details of process needs to be saved before switching.
7. Complex Compiler Optimization.

Question 3

Why not Zero Registers?

Answer 3

If we have zero registers, the CPU will have to access memory directly every single time which will have high latency.

Question 4

Why do we unsigned variants for LH and LB but not for SH and SB?

Answer 4

Unsigned variants are available for LH and LB because we need to identify how we are going to fill the remaining bit values in the register. We don’t need to worry about this while storing values.

Question 5

Moore’s Law

Answer 5

The number of transistors per unit cost doubles approximately every two years.

Question 6

Dennard Scaling

Answer 6

Power density remains constant as transistors get smaller.

Power = Capacitance x Voltage^2 x Frequency

Question 7

When did Dennard Scaling end and why?

Answer 7

Ended in 2006. Due to the fact that the Leakage Current and Heat issues due to transisor miniaturization, making scaling of frequency impractical.

Also due to rise of multi-core systems.

Question 8

Utilization Wall

Answer 8

Refers to the fact that even though Moore’s law allows us to add more transistors to a chip, we cannot use all of them at once due to power and thermal constraints.

Question 9

What are the benefits of Digital Systems?

Answer 9

1. They are restorative as Noise is cancelled at each digital components.
2. Complex design can be constructed on the abstraction of digital behaviour.

Question 10

What are the processor digital constraints?

Answer 10

1. Chip Area
2. Attainable Clock Speed.
3. Instruction Level Parallelism
4. Amdahl’s Law

Question 11

Limitations of the processor digital constraints?

Answer 11

1. Chip size may be smaller.
2. Clock speed may be limited.
3. Work per cycle may be limited.
4. Benefits of more cores may be limited.

Question 12

Performance Measures - What is Latency, Throughput?

Answer 12

Latency - Delay from when an Input enters the system until it’s associated output is produced.

Throughput - Rate at which Outputs are produced in a given time.

Question 13

What are the two different type of Circuits?

Answer 13

Combinational Circuits and Sequential Circuits.

Combinational Circuits:
1. Contains no memory (“no state”).
2. Outputs soley depend on the inputs.

Sequential Circuit
1. Has memory (“state”)
2. Memory is updated by the output of Combinational Circuit.

Question 14

What is Propagation Delay?

Answer 14

Maximum time it takes for a change in input to change the output.

Question 15

What is Contamination Delay?

Answer 15

Minimum time it takes for a change in input to start changing the output.

Question 16

What is Setup Time?

Answer 16

Time before the clock edge the input must be stable.

Question 17

What is Hold Time?

Answer 17

Time after the clock edge the input must be stable.

Question 18

What is Additive Delay?

Answer 18

The total of all circuit delays. This includes the extra delay from interconnects, buffering, and loading.

Question 19

When can you say a good circuit has low propagation delay?

Answer 19

Faster Inputs
Higher Performance

Question 20

What is Synchronous Sequentail Circuit?

Answer 20

All operations are aligned to a shared clock signal. In a Synchronous circuit, the clock period must be long enough to allow the signal to propagte through the critical path and for the state to be updated reliably.

All paths must be shorter than the clock spped.

Question 21

Complex ISA can slow down the clock. Why?

Answer 21

Instruction length can be very complex with variable length and many different formats.

This will require more complex and time-consuming decoding logic in the CPU.

The more complex, the longer it takes, limiting how fast the CPU can complete the task.

Question 22

Benefits of Pipelining

Answer 22

Increased throughput and Improved Hardware utilization.

Question 23

Drawbacks of Pipelining

Answer 23

Increased Latency (however increased throughput usaully outweighs the slight increase in latency)

Increased Hardware Complexity.

Question 24

Latency related Formulas

Answer 24

Combinational Circuit - Latency = Propagation Delay

K-Stage Pipeline - Latency = K * Clock Period

Question 25

Throughput related Formulas

Answer 25

Combinational Circuit - Throughput = 1 / Propagation Delay K-Stage Pipeline - Throughput = 1 / Clock Period

Question 26

When does pipeline become non-deterministic?

Answer 26

The time a stage takes to complete varies. This can happen due to things like memory access or complex combinational logic that takes different amount of time depending on the input.

Question 27

What is Elastic Pipeline?

Answer 27

Elastic pipelines are pipelines that dynamically adjustable pipelines that ensures correct results are provided regardless of unknown latency using mechanisms like FIFO registers and maintining equal number of pipeline registers across all stages.

Question 28

Little's Law?

Answer 28

L = lambda * W L -> No of requests in the system Lambda - Throughput W - Latency

Question 29

Von Neumann Model

Answer 29

All modern computers are based on the Von Neumann Model. Components: Main Memory - Data and Programs are held Processing Unit - Program Counter and ALU Storage and I/O - For communication

Question 30

Classic RISC Pipeline

Answer 30

Fetch, Decode, Execute, Memory, and Writeback

Question 31

Constraints in designing Microprocessor

Answer 31

1. Circuit Timing 2. Memory Access Latency

Question 32

What is an Ill-Formed Pipeline?

Answer 32

Ill-Formed Pipeline states that there are inconsistency in the total number of registers used in all paths.

Question 33

We have SRA, SRL, and SLL. Why is there no SLA?

Answer 33

SRL (Shift Right Logical) - Fills the leftmost bits with 0s, regardless of the original sign bit. SRA (Shift Right Arithmetic) - Fills the leftmost bits with the Most Significant Bit (MSB) (preserving sign for negative numbers). SLL is sufficient for left shifts because it already fills the least significant bits with 0s. If an SLA were introduced, it would try to preserve the sign bit (like SRA), but this is unnecessary in left shifts leading to change of value in the register leading to incorrect results.