CPU Flashcards
(41 cards)
What registers are involved in Von Neumann architecture?
Memory Address Register
Memory Data Register
Program Counter
Accumulator
Current Instruction Register
What does the Program Counter do?
Stores the location of the next instruction to execute
What does the Memory Address Register do?
Stores the address of a location in memory that is currently being read from or written to
What does the Memory Data Register do?
Holds the data that has just been retrieved from memory or the data that is about to be written to memory
What does the Accumulator do?
Stores to results of calculations from the Arithmetic Logic Unit (ALU)
What does the Current Instruction Register do?
Stores the current instruction being executed in the CPU
What other components are part of the Von Neumann architecture?
Decode Unit,
Control Unit,
Arithmetic Logic Unit,
Busses,
Cache
What are the 3 Busses in Von Neumann architecture?
Address Bus,
Data Bus,
Control Bus
What does the Decode Unit do?
Decodes the current instruction to be executed
What does the Control Unit do?
Controls the flow of data in the CPU by telling each component what to do and when to do it e.g. telling memory to read at this exact moment
What does the Arithmetic Logic Unit do?
Performs arithmetic operations and logical operations on data, allowing the CPU to perform many calculations
What does the Cache do?
Stores frequently used instructions and data close to the CPU for much faster access compared to RAM, because it is so much closer to the proccessing unit
What are the 3 factors that determin CPU performace?
Cache Size,
Clock Speed,
Number of Cores
How does Cache Size affect CPU performace?
Larger cache size increases CPU performance by allowing for more frequently used instructions and data to be held much closer to the CPU for much faster access
How does Clock Speed affect CPU performance?
A higher clock speed increases the number of fetches the CPU can make per second increasing performance as more instructions can be completed faster as more a fetched
How does Number of Cores affect CPU performance?
A larger number of cores can increase performance by allowing the CPU to proccess multiple threads at the same time, but is not just a simple increase as the more cores there are the more time they have to spend communicating and coordinating with each other
Describe the entire Fetch-Decode-Execute Cycle
Fetch - Program Counter gives its location data to the Memory Address Register. The Program Counter then increments by 1. The Memory Address Register sends the address it has along the address bus to memory to read the instruction at that location. The Control Unit tells the memory to read now and the data is put on the data bus to be moved into the Memory Data Register. From there the instruction is moved into the Current Instruction Register to be decoded and executed.
Decode - The instruction is decoded by the Decode Unit, to know exactly what to do next
Execute - The Control Unit uses the decoded instruction and executes the instruction e.g. reading a value from memory into the accumulator
What is an instruction set?
A list of machine code instructions a specific CPU can recognise
What are some other factors that affect CPU performance?
Width and speed of the Data bus
Size of registers
How does width on the data bus affect CPU performance?
larger width increases performance as more data and instructions can be given to the CPU at once
How does speed on the data bus affect CPU performance?
Data fetched from memory reaches the CPU much faster, with higher data bus speeds, causing the CPU to stall for less time waiting for data and instructions increasing CPU performance
How does register size affect CPU performace?
Larger register sizes can allow the CPU to hold more data and interact with more memory as addresses stored can be larger, this allows the CPU to accept more data at once as well to be worked on, increasing performance
What is Pipelining?
While one instruction is being executed another one can be being decoded and another being fetched, rather than waiting for one instruction to be fully executed then fetching, decoding and executing the next one, making the CPU much faster
What is a problem caused by a branch for pipelining?
When a branch occurs the Pipeline may have to be flushed as the next instructions that are in the pipeline aren’t supposed to be executed, however they are still put into the pipeline as if its a conditional branch the branch may not occur and the CPU can keep going without having to flush the pipeline
