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Module 4 > Day 5 > Flashcards

Day 5 Flashcards

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1
Q

Bus

A

connection between computer systems components that moves data back and forth

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2
Q

What three lines are busses broken into

A

address, data, and control

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3
Q

Address Line

A

indicates the location data should be read from or written to.

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4
Q

Data Line

A

Transfers data

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5
Q

Control Line

A

Carries command and status signals (e.g. read/write commands, interrupts, and synchronization.

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6
Q

What is the concept of System on a Chip (SoC)

A

processor, memory, and a bus on the same chip

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7
Q

What is a bridge?

A

allows communication between dissimilar buses. since buses communicate at different speeds and in different languages; bridge functions as a translator.

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8
Q

I/O modules

A

interface between processor, memory, and one or more peripheral devices. similar to a CPU except they only have one purpose

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9
Q

device interface

A

physical connector attaching peripheral devices to the computer ; aka ports.
consists of 3 lines: control, data, and status.
has the same name of the bus

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10
Q

Bus topology

A

arrangement of connections between computer system components. 2 different types: multipoint bus and point to point bus

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11
Q

Multipoint bus

A

connects more than two components together. Control line needed since there is a common pathway

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12
Q

How is control accomplished with a Multipoint bus

A

using a master/slave (LMFAO) or assigned priorities

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13
Q

Point-to-point bus

A

connects only two components together. ie RAM to Northbridge where there is a direct connection between the two components.

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14
Q

Bus arbitration

A

system for resolving bus control conflicts by assigning priorities to bus control requests in a multipoint bus topology where there is more than one connected device. There are 3 different types

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15
Q

Daisy chain

A

devices are connected in series, requesting device closest to the arbiter gets the bus then they give access to the devices further away from the arbiter

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16
Q

Centralized Parallel

A

requests for bus access are sent via directed control lines from each device to a centralized arbiter. arbiter compares device priorities and provides bus grant on the appropriate devices control line.

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17
Q

Distributed using self-selection

A

all devices communicate bus requests to each other. highest priority is granted access. Priority determined by the device code in the bus access request.

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18
Q

Bus protocol

A

method that computer components use to transmit data between the sender and receiver. 2 different types: serial and parallel.

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19
Q

Serial Communication

A

sends data one bit at a time. relies on handshaking for synch (asynchronous)

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20
Q

Parallel Communication

A

sends a group of bits via multiple data lines. relies on clock signal for synch (synchronous). It’s faster but only for short distances. Also costly due to crosstalk

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21
Q

Handshaking

A

series of steps to coordinate asynchronous communication in which sender and receiver proceed to the next step only when both parties agree.

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22
Q

Steps for a handshake

A
  1. bus control is active and data memory address is put on the address line.
  2. memory system puts required data on data line
  3. data is acknowledged via control line
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23
Q

Serial Port

A

RS-232 point to point serial communications

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24
Q

Parallel Port

A

IEEE-1284 point to point parallel communications

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25
Small computer system interface (SCSI)
multi-point parallel bus with devices daisy chained together. commonly used commercially for hard disk drives and tape drives.
26
Serial attached SCSI (SAS)
point-to-point serial bus built on the SCSI standard.
27
Parallel Advanced technology attachment (PATA)
multi-point parallel bus AKA integrated drive electronics (IDE). used in older computers to connect hard/floppy disks
28
Serial Advanced Technology Attachment (SATA)
Point-to-point serial bus successor to PATA allows hot swap connection of most types of mass storage devices. (hard disks, ssds, and optical drives)
29
Peripheral Component interconnect express (PCIe)
An expansion bus that uses channeled point to point serial communications. found on north bridge for graphic cards and south bridge for sound and other i/o cards.
30
Universal Serial Bus (USB)
point-to-point serial bus that can connect many types of peripherals.
31
Video Graphics Array (VGA)
Standard analog video interface for color resolution
32
Digital Video Interface (DVI)
Video interface designed for digital to digital connection
33
High-def multimedia interface (HDMI)
high res multimeida (video/audio) interface that includes digital rights management for copy protections
34
DisplayPort (DP)
digital display interface for connecting a video source to a display device. first to use display interface to use packetized data.
35
Memory mapped I/O
I/O scheme in which portions of RAM are assigned to I/O devices, and reads and writes to those addresses are interpreted as commands to the I/O device. commonly used for device driver communication to a device in the form of instructions
36
Programmed I/O
(Polling) process of periodically checking I/O device status to determine a need to service the device. - works well with slow devices - has most overhead - tests device's status before transferring each data byte - provides data rates that are a bit slower.
37
interrupt-driven I/O
divided into two categories: interrupts and exceptions. they are used to interrupt normal operations of a program executing on the processor when a problem occurs.
38
Interrupt
event typically triggered by an I/O device. asynchronous events since they occur at random times.
39
Exception
an event resulting from the execution of an instruction of the current program; therefore a synchronous event.
40
What are the three classes of exceptions?
1. Traps: software invoked exceptions 2. Faults: Occur when attempting division by zero or when accessing memory incorrectly (page fault) 3. Aborts: used to report sever errors, such as hardware errors, and inconsistent or illegal values in system tables
41
Direct Memory Access (DMA)
mechanism that provides a device controller with the ability to transfer data directly to or from memory without involving the processor. - has low latency - fastest transfer rates, but at cost of additional hardware complexity.
42
Memory Architecture
consists of methods used to implement computer data storage.
43
Volatility
the persistence of data in memory unit when power is lost.
44
Latency
the time it takes memory to output set data once the memory controller receives data request. Measured in bus clock cycles.
45
Throughput
rate at which data is loaded from and stored to memory; aka memory bandwidth. Measured in bits per second.
46
Buffering
act of storing data in a region of physical memory called a buffer.
47
Principle of Locality
states the same values, or related storage locations; accessed frequently or sequentially. Two ways to do so: temporal and spatial
48
Temporal locality
referencing the same data often (e.g. loop)
49
Spatial locality
referencing data elements in close storage locations (sequence)
50
Translation Lookaside Buffer (TLB)
translates virtual memory addresses (called a page) to physical memory (called a frame)
51
What is a TLB hit?
if TLB has made that translation, then it provides the physical address to the cache
52
What is a TLB miss?
if the TLB has not made that translation, and the TLB must go out to the page table in RAM to retrieve the physical address.
53
Cache hit
when the cache checks to see if it contains data requested and it does. When it doesn't its a cache miss
54
Direct Mapped
each memory address is mapped to one cache address
55
Associative
allows a memory block to be stored in one of several cache blocks.
56
Victim block
When a block in a cache is selected for replacement
57
Dirty block
when cache data has been modified from its original version in RAM
58
Methods of replacement
Less Recently used (LRU) First in, First out (FIFO) Random
59
Write-through
updates cache and main memory (RAM) simultaneously during every write.
60
Write-back
updates the block in main memory when the cache block becomes a victim block.
61
Multi-level Cache
reduces the cache miss penalty by adding additional levels to the hierachy.
62
Harvard Cache
independent cache for data and instructions
63
Unified cache
holds both instructions and data
64
Primary memory
consists of mostly medium speed memories that hold code for boot-up or to hold program during execution.
65
Random Access Memory (RAM)
allows for reading and writing data. | 2 types: static and dynamic
66
Static RAM (SRAM)
each cell is made of a 4 to 10 transistor D flip-flop (latch) circuit that holds data as long as there is power.
67
Dynamic Ram (DRAM)
each cell is made of one transistor or one capacitor
68
Read only memory (ROM)
non-volatile and non as firmware. (used in micro-controllers, cell phones, RFID tags, BIOS/UEFI, etc) 3 types
69
Progammable ROM
programmed once for read-only access either during manufacture or by the customer using a special PROM writer.
70
Erasable Programmable ROM
programmed by applying a slightly higher than normal voltage, when the voltage is removed, the charge is trapped in the transistor gate.
71
Electrically Erasable Programmable
can be erased and reprogrammed, one byte at a time.
72
secondary memory
aka secondary storage and is non-volatile. magnetic disks are most common
73
magnetic disks
form of magnetic media where data is stored by leaving magnetic charges on magnetizable media surface
74
Low-level format
creates tracks and sectors on blank platters
75
Track
concentric circle on the platter
76
cylinder
combination of all the tracks
77
High-level format
done when OS is installed. creates the hard drive's partitioning scheme and assigns the file system to manage the storage, tracking, and retrieval of files.
78
What way to disk platters spin?
clockwise at a Constant Angular Velocity (CAV); measured in revolutions per minute
79
Common RPMS for consumer grade
desktop 4800, 5400, 7200 | laptop 4200, 5200, 5400, 7200
80
What is disk performance measured by
``` spin-up time seek time rotational latency transfer time disk access time ```
81
Solid State Drive (SSD)
flash memory is used to produce this, and is similar to magnetic disk. Built on arrays of NAND Or NOR-based memory circuits where data persists after power is removed. Have no moving parts
82
Why has the use of flash memory increased since 2005
improved reliability and increased storage capacity.
83
Logical Block Addressing (LBA)
Simple linear addressing scheme where each 512B or 4KB block of data is located by an integer index.
84
Redundant Arrays of Inexpensive Disks (RAID)
uses collection of disks to improve reliability and performance.
85
RAID 0
allows for improved performance using drive spanning to stripe data across many disks. requires minimum of 2 drives and doesn't allow disk failures.
86
RAID 1
allows improved reliability by using disk mirroring that duplicates the data from one disk to many disks. Minimum of 2 drives and allows for one disk in each pair to fail.
87
RAID 5
allows improved reliability by using parity and improved performance by using drive spinning. Parity used to error detection. uses XOR to calculate parity. Minimum of 3 devices and allows for any one disk to fail. Recommended for file, application, email and web servers where performance and data storage are a concern
88
External Memory
alternate location for storing data that exists outside of a computer's main memory.
89
Magnetic Tape
strip of film with a magnetic coating allowing for data storage. Strip can be hundreds of feet long and is wound onto a reel.
90
Optical Discs
made out of an aluminum film covered in a plastic casing. A low power laser is used to read and write data. Data is stored by creating deprecations in the medium called pits and creating lands between each pit.
91
Constant Linear Velocity (CLV)
The rate at which sectors pass over the laser remains equal regardless of head position.
92
What way does the disc spin looking at the disc from the bottom?
counter-clockwise

Module 4 (5 decks)

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