Definitions Flashcards
(123 cards)
1
Q
RP
A
2
Q
PVG
A
3
Q
OSPM
A
3
Q
NVDIMM
A
4
Q
SoC
A
5
Q
PPOG
A
6
Q
PCH
A
7
Q
UPI
A
8
Q
SPC
A
8
Q
UART
A
9
Q
QPI
A
9
Q
DPS
A
10
Q
DIMM
A
10
Q
SR
A
11
Q
DR
A
12
Q
MT/S
A
13
Q
TDP
A
14
Q
AP/SP
A
14
Q
SNC
A
15
Q
DC-SCM
A
16
Q
L1
A
17
Q
L3
A
17
Q
UMA
A
17
Q
NUMA
A
18
L0
19
SBSP
19
L2
20
LEPs
21
PLD
22
BKC
23
FSP
23
AGESA
23
PBSP
24
EC
24
vBIOS
25
ME
26
IEH
27
SCI
28
HEST
29
APEI
30
WHEA
31
CMCI
31
EMCA
32
ASIC
32
PPR
32
GDDR
33
FPGA
33
PCU
34
NMI
35
DCB
35
S3M
35
PFR
36
DC-MHS
36
IBL
37
GbE
38
DMI
39
PRoT
40
SBI
40
FRP
40
EDSFF
41
MRC
42
IPMI
43
GPE
43
SCI
44
IRQ
45
SDSi
45
TDX
46
BTG
46
FIT
46
SPDM
47
ACM
48
TME-MT
48
TME
49
SGX
50
MKTME
50
SEAAM
50
SEAMRR
51
ACTM
52
TDVF
53
VMM
54
I2C
55
ASD
55
PECI
56
I3C
57
SPS
58
BASD
58
MCTP
58
PMT
58
BAFI
58
ACD
59
CHA
60
MC
61
LLC
62
M2M
63
2LM
64
B2CMI
65
SNC
66
CPLD
66
CSME
67
DICE
68
MBIST
69
LBIST
70
CoT
71
SIO
72
APU
73
NIC
74
IaaS
75
RTU
76
HMAC
77
AKC
Authentication Key Certificate
-a key written to internal NVRAM that is used to authenticate a capability-specific activation payload, retrieve by sending an IOCTL HMAC
78
CAP
Capability Activation Payload
-a token authenticated using AKC and applied to the CPU configuration to activate a new feature, done by sending an IOCTL HMAC
79
QAT
80
DLB
81
DSA
82
IAX
83
NPEM
84
NTB
A device that forwards PCIe traffic between busses like a bridge. Two main purposes: to allow inter-processor communication between different hosts, and to ensure address domain isolation. Non-transparent: one host cannot enumerate or access directly other host PCIe hierarchy, host on side of the bridge will not have visibility to complete memory I/O space on the other side.
85
RCiEP
Embedded endpoint that is implemented on the root complex internal logic. Contains the root port and is used to declare the Root Complex Integrated Endpoints support by the Root Complex Event Collector on the same logical bus on which the Root Complex Event Collector is located.
86
RCEC
PCIe device that is responsible for collecting and logging error messages from PCIe devices. Part of the PCIe Advanced Error Reporting (AER) feature set, implemented as part of the root complex(PCIe device that connects the CPU to the PCIe fabric). Detects uncorrectable errors, correctable errors, and fatal errors.
87
DVSEC
A register locator that acts as a link to access memory-mapped registers. It is available in the configuration space of a device and is used to define a vendor-specific extended capabilities that is not tired to the vendor ID of the component.
88
SRAT
Provides the boot time description of the processor and memory ranges belonging to a system locality.
89
HMAT
Describes memory attributes, such as memory side cache attributes and bandwidth and latency details, related to Memory Proximity Domains. The OS uses this to optimize the system memory configuration.
90
CDAT
Describes performance characteristics of a CXL device or a DXL switch.
