Digital Systems T1

Question 1

The Verilog HDL is case-sensitive.

Answer 1

True

Question 2

Which HDL description or model is a one-to-one match with the schematic diagram of a logic circuit?

Answer 2

Structural

Question 3

The Verilog HDL has gate-level primitives defined in the language standard and recognized by the compiler/synthesizer.

Answer 3

True

Question 4

The binary/logic operators in Verilog:

Answer 4

Use special characters

Question 5

The first port in the port list of a Verilog gate level primitive is:

Answer 5

the one and only output

Question 6

Does behavioral description give any hints about how the circuit should be implemented?

Answer 6

No

Question 7

The statements in an always block are executed

Answer 7

whenever one or more signals in the sensitivity list change

Question 8

The statements in a procedural block (always or initial in verilog) are executed

Answer 8

Sequentially

Question 9

We can use functional description inside a procedural block

Answer 9

True

Question 10

We can instantiate modules inside a procedural block

Answer 10

False

Question 11

A test bench can be synthesized

Answer 11

Flase

Question 12

A test bench has no input and outputs

Answer 12

True

Question 13

Exhaustive verifications applies

Answer 13

All possible input combinations

Question 14

The initial verilog procedural block is executed

Answer 14

Only once

Question 15

The signals assigned a value inside a procedural block (always or initial verilog) have to declared of type

Answer 15

Reg

Question 16

Which is the first deign step in the design flow?

Answer 16

Design entry/capture

Question 17

Which type of languages can be describe both concurrent and sequential events?

Answer 17

hardware description languages (HDLs)

Question 18

Which simulation type is more accurate i.e. models real logic circuits more accurate?

Answer 18

Timing simulation

Question 19

which HDL was created first for documentation purposes?

Answer 19

VHDL

Question 20

Which language was created first for modeling/simulation purposes?

Answer 20

Verilog

Question 21

High impedance or tri-stated outputs are used to transfer data

Answer 21

From multiple sources to one destination

Question 22

VHDL entity contains the component interface information

Answer 22

True

Question 23

VHDL logic operators use:

Answer 23

Letters names, such as AND, OR, XOR, ect…

Question 24

VHDL does NOT have built-in gate-level primitives

Answer 24

True

Question 25

A VHDL component is comprised of

Answer 25

One entity and one or more architectures

Question 26

All project files that contain descriptions belong automatically to the work library

Answer 26

True

Question 27

The sensitivity list should contain all signals used inside the process on the right-hand-side of assignments

Answer 27

True

Question 28

if-else and/or case statements can be nested

Answer 28

True

Question 29

Behavioral description uses

Answer 29

Procedural statements

Question 30

The statements in a VHDL process are executed

Answer 30

Sequentially

Question 31

In Verilog the size of an instance using a parameterized module can be chosen

Answer 31

by providing a new value for the parameter(s) at the time of instantiation

Question 32

In an RCA the carry-outs ripple (propagate) from the least significant bit (LSB) position to the most significant (MSB)

Answer 32

True

Question 33

Multi-bit signals in verilog are described as

Answer 33

Vectors

Question 34

In named (or explicit) association or (port mapping) the order of associations

Answer 34

Does NOT matter

Question 35

To create paramterized descriptions using module instances

Answer 35

We need to use the GENERATE FOR loop/construct

Question 36

To create generic descriptions using component instances

Answer 36

We can use the VHDL FOR GENERATE loop in the concurrent block of code

Question 37

In a RCA the cout is known after all carries have propagated (rippled through) from:

Answer 37

the LSB to the MSB position

Question 38

multi-bit signals in VHDL are described as:

Answer 38

Vectors

Question 39

in VHDL a generic component can be resized from the default value(s) at instantiation time by

Answer 39

Providing another value for generics

Question 40

In VHDL generic mapping maps

Answer 40

Generic to positive integer values

Question 41

At instantiation time, the value of a parameter in verilog can be specified

Answer 41

In more than one way

Question 42

The VHDL FOR GENERATE loop can only be used in a procedural block of code

Answer 42

False

Question 43

The verilog GENERATE FOR loop can only be used in a concurrent block of code

Answer 43

True

Question 44

The GENERATE FOR loop in verilog allows description of a circuit with arbitrary structure

Answer 44

False

Question 45

the FOR GENERATE loop in VHDL allows the description with a repetitive (period) structure

Answer 45

True

Question 46

A 2-variable function can be implemented using 4to1mux by

Answer 46

Connecting the 2-vairables/inputs to the data of the mux

Question 47

In the implementation of a function (CL circuit) we can combine gates and muxes

Answer 47

True

Question 48

Expansion by different variables/intputs may result in co-factors of different complexities

Answer 48

True

Question 49

Any binary function can be implemented

Answer 49

True

Question 50

Higher-order multiplexers can be built using lower order multiplexers. ultimately at the lowest level of the implementation one would use 2-to-1 muxes

Answer 50

True

Question 51

In a FPGA LUT the data inputs of the multiplexer are driven by:

Answer 51

Values stored in storage elements

Question 52

The application of Shannon's expansion theorem involves the following steps: 1 - Expansion - if necessary to produce terms that contain the true and complemented values of the expansion variable 2 - Re-arrangement of the function form 3 - Simplification of the co-factors - if necessary

Answer 52

True

Question 53

a not gate can be implemented using 2to1mux by:

Answer 53

Connecting the NOT input to the select input of the mux and its data input 0 connected to 1 and 1 connected to 0 respectively

Question 54

If we expand a function by 2 variables, we need at least a:

Answer 54

4to1mux

Question 55

The canonical form of function is

Answer 55

The SOP of all the terms for which the function is 1