E7 - PRACTICAL CIRCUITS [8 Exam Questions - 8 Groups] Flashcards
Which of the following is a bistable circuit?
A. An “AND” gate
B. An “OR” gate
C. A flip-flop
D. A clock
C. A flip-flop
How many output level changes are obtained for every two trigger pulses applied to the input of a T flip-flop circuit?
A. None
B. One
C. Two
D. Four
C. Two
Which of the following can divide the frequency of a pulse train by 2?
A. An XOR gate
B. A flip-flop
C. An OR gate
D. A multiplexer
B. A flip-flop
How many flip-flops are required to divide a signal frequency by 4?
A. 1
B. 2
C. 4
D. 8
B. 2
Which of the following is a circuit that continuously alternates between two states without an external clock?
A. Monostable multivibrator
B. J-K flip-flop
C. T flip-flop
D. Astable multivibrator
D. Astable multivibrator
What is a characteristic of a monostable multivibrator?
A. It switches momentarily to the opposite binary state and then returns, after a set time, to its original state
B. It is a clock that produces a continuous square wave oscillating between 1 and 0
C. It stores one bit of data in either a 0 or 1 state
D. It maintains a constant output voltage, regardless of variations in the input voltage
A. It switches momentarily to the opposite binary state and then returns, after a set time, to its original state
What logical operation does a NAND gate perform?
A. It produces a logic “0” at its output only when all inputs are logic “0”
B. It produces a logic “1” at its output only when all inputs are logic “1”
C. It produces a logic “0” at its output if some but not all of its inputs are logic “1”
D. It produces a logic “0” at its output only when all inputs are logic “1”
D. It produces a logic “0” at its output only when all inputs are logic “1”
What logical operation does an OR gate perform?
A. It produces a logic “1” at its output if any or all inputs are logic “1”
B. It produces a logic “0” at its output if all inputs are logic “1”
C. It only produces a logic “0” at its output when all inputs are logic “1”
D. It produces a logic “1” at its output if all inputs are logic “0”
A. It produces a logic “1” at its output if any or all inputs are logic “1”
What logical operation is performed by a two-input exclusive NOR gate?
A. It produces a logic “0” at its output only if all inputs are logic “0”
B. It produces a logic “1” at its output only if all inputs are logic “1”
C. It produces a logic “0” at its output if any single input is a logic “1”?
D. It produces a logic “1” at its output if any single input is a logic “1”?
C. It produces a logic “0” at its output if any single input is a logic “1”?
What is a truth table?
A. A table of logic symbols that indicate the high logic states of an op-amp
B. A diagram showing logic states when the digital device’s output is true
C. A list of inputs and corresponding outputs for a digital device
D. A table of logic symbols that indicates the low logic states of an op-amp
C. A list of inputs and corresponding outputs for a digital device
What is the name for logic which represents a logic “1” as a high voltage?
A. Reverse Logic
B. Assertive Logic
C. Negative logic
D. Positive Logic
D. Positive Logic
What is the name for logic which represents a logic “0” as a high voltage?
A. Reverse Logic
B. Assertive Logic
C. Negative logic
D. Positive Logic
C. Negative logic
What is an SR or RS flip-flop?
A. A speed-reduced logic device with high power capability
B. A set/reset flip-flop whose output is low when R is high and S is low, high when S is high and R is low, and unchanged when both inputs are low
C. A speed-reduced logic device with very low voltage operation capability
D. A set/reset flip-flop that toggles whenever the T input is pulsed, unless both inputs are high
B. A set/reset flip-flop whose output is low when R is high and S is low, high when S is high and R is low, and unchanged when both inputs are low
What is a JK flip-flop?
A. A flip-flop similar to an RS except that it toggles when both J and K are high
B. A flip-flop utilizing low power, low temperature Joule-Kelvin devices
C. A flip-flop similar to a D flip-flop except that it triggers on the negative clock edge
D. A flip-flop originally developed in Japan and Korea which has very low power consumption
A. A flip-flop similar to an RS except that it toggles when both J and K are high
What is a D flip-flop?
A. A flip-flop whose output takes on the state of the D input when the clock signal transitions from low to high
B. A differential class D amplifier used as a flip-flop circuit
C. A dynamic memory storage element
D. A flip-flop whose output is capable of both positive and negative voltage excursions
A. A flip-flop whose output takes on the state of the D input when the clock signal transitions from low to high
For what portion of a signal cycle does a Class AB amplifier operate?
A. More than 180 degrees but less than 360 degrees
B. Exactly 180 degrees
C. The entire cycle
D. Less than 180 degrees
A. More than 180 degrees but less than 360 degrees
What is a Class D amplifier?
A. A type of amplifier that uses switching technology to achieve high efficiency
B. A low power amplifier using a differential amplifier for improved linearity
C. An amplifier using drift-mode FETs for high efficiency
D. A frequency doubling amplifier
A. A type of amplifier that uses switching technology to achieve high efficiency
Which of the following forms the output of a class D amplifier circuit?
A. A low-pass filter to remove switching signal components
B. A high-pass filter to compensate for low gain at low frequencies
C. A matched load resistor to prevent damage by switching transients
D. A temperature-compensated load resistor to improve linearity
A. A low-pass filter to remove switching signal components
Where on the load line of a Class A common emitter amplifier would bias normally be set?
A. Approximately half-way between saturation and cutoff
B. Where the load line intersects the voltage axis
C. At a point where the bias resistor equals the load resistor
D. At a point where the load line intersects the zero bias current curve
A. Approximately half-way between saturation and cutoff
What can be done to prevent unwanted oscillations in an RF power amplifier?
A. Tune the stage for maximum SWR
B. Tune both the input and output for maximum power
C. Install parasitic suppressors and/or neutralize the stage
D. Use a phase inverter in the output filter
C. Install parasitic suppressors and/or neutralize the stage
Which of the following amplifier types reduces or eliminates even-order harmonics?
A. Push-push
B. Push-pull
C. Class C
D. Class AB
B. Push-pull
Which of the following is a likely result when a Class C amplifier is used to amplify a single-sideband phone signal?
A. Reduced intermodulation products
B. Increased overall intelligibility
C. Signal inversion
D. Signal distortion and excessive bandwidth
D. Signal distortion and excessive bandwidth
How can an RF power amplifier be neutralized?
A. By increasing the driving power
B. By reducing the driving power
C. By feeding a 180-degree out-of-phase portion of the output back to the input
D. By feeding an in-phase component of the output back to the input
C. By feeding a 180-degree out-of-phase portion of the output back to the input
Which of the following describes how the loading and tuning capacitors are to be adjusted when tuning a vacuum tube RF power amplifier that employs a pi-network output circuit?
A. The loading capacitor is set to maximum capacitance and the tuning capacitor is adjusted for minimum allowable plate current
B. The tuning capacitor is set to maximum capacitance and the loading capacitor is adjusted for minimum plate permissible current
C. The loading capacitor is adjusted to minimum plate current while alternately adjusting the tuning capacitor for maximum allowable plate current
D. The tuning capacitor is adjusted for minimum plate current, while the loading capacitor is adjusted for maximum permissible plate current
D. The tuning capacitor is adjusted for minimum plate current, while the loading capacitor is adjusted for maximum permissible plate current
















