Electronic- Semiconducting Processing

Question 1

What does semiconductor technology require?

Answer 1

Growth, control and patterning of semiconductor layers of the very highest quality. Relies on having extremely high quality substrates upon which the devices are fabricated. These are semiconductor wafers and are generally single crystals

Question 2

Range of sizes of wafers

Answer 2

From 61cm diameter for large scale Si device to 5cm for specialist materials

Question 3

What are wafers cut from?

Answer 3

Larger boules of single crystal semiconductor material

Question 4

Czochralski growth of boules

Answer 4

A Czochralski puller holds a semiconductor crystal melt in a rotating crucible (boron nitride). A rotating crystal seed is lowered into contact with melt. As seed is pulled up gradually additional crystallisation from melt is observed. Rotations prevent temperature gradients due to convection currents

Question 5

What is needed for high quality Czochralski growth?

Answer 5

Temperature control using heating and insulation, and rate of pulling critical. Mainly to control shale of crystallisation front which is found above melt line due to surface tension

Question 6

Shapes of crystallisation front for Czochralski

Answer 6

Ideally convex from crystal so that crystal diameter will increase and dislocations will grow out.
If concave the crystal diameter will decrease and dislocation will grow towards the centre axis

Question 7

Problem with III-V materials for Czochralski growth

Answer 7

Can have an element with high vapour pressure leading to selective loss and non-stoichiometric melt. To solve, melt has a layer of liquid boron oxide above. This is liquid encapsulated Czochralski growth

Question 8

How are wafers made from boules?

Answer 8

Boules sown inti wafers (boules aligned using X-ray diffraction before cut). Cut wafers then check-mechanically polished so roughness <1nm. Oxidised during polishing since non-crystalline oxide easier to remove by polishing (fixed thickness). Final oxide layer removed in growth chamber to expose underlying crystal lattice. Polishing platters move in double orbital motion to ensure <20nm flatness over entire wafer

Question 9

Wafer shape

Answer 9

Circular but with 2 straight edges included. One is long (major flat) which identifies a particular crystallographic direction. One is short (minor flat) which is used to denote doping type of semiconductor

Question 10

Crystal structures of semiconductors

Answer 10

Si and Ge diamond

Most III-V have zinc blend which is similar to diamond and is effectively 2 tandem fcc lattices for the 2 element groups

Question 11

What is epitaxial growth?

Answer 11

Grown layers take on crystal arrangement of underlying surface.

Question 12

Why do semiconductor devices rely on well-ordered single crystal layers?

Answer 12

Reliable electron scattering
Controlled electronic properties
Thus need for epitaxial growth

Question 13

What does epitaxy of more than one material lead to?

Answer 13

This is heteroepitaxy and involves a mismatch in materials lattice constants. Leads to strain developing which will change the band gaps

Question 14

Set up for molecular beam epitaxy

Answer 14

Separate effusion cells contain the various materials required for semiconductor growth. Temperature of each cell precisely monitored to achieve correct growth conditions. Shutter on each cell controls introduction of each material. Wafer is in the line of sight of all effusion cells.

Question 15

Conditions in MBE

Answer 15

System under ultra-high vacuum with pressure <10^-9mbar. Mean free path of atoms from effusion cells is much greater than cell to wafer separation. Wafer heated to a process and material-dependent temperature

Question 16

Why is heating of wafer controlled in MBE?

Answer 16

It controls the degree of surface mobility of incident atoms. Different growth conditions result from high/low surface mobility. Too high a temperature leads to selective loss of a particular element and a change in material stoichiometry and properties

Question 17

How do incident atoms ideally add to surface in MBE?

Answer 17

Add to surface one atomic layer at a time

Question 18

How to monitor growth in MBE

Answer 18

Reflection high energy electron diffraction (RHEED). Uses diffraction of electron beams having 10-30keV energies. Diffracted beams incident on fluorescent screen and detected using CCD camera or photomultiplier. Diffraction pattern gives information about crystal structure.

Question 19

How to know number of grown atomic layers from RHEED

Answer 19

Any particular diffraction spot oscillates in intensity as each successive layer is formed. Count number of RHEED oscillations over time to know how many atomic layers grown (peak to peak)

Question 20

Methods of local doping

Answer 20

Ion implantation

Diffusion

Question 21

Ion implantation

Answer 21

Most common. Ions of dopant element accelerated towards semiconductor substrate. Ion energies 10-500keV. Results in graded dopant profile and controllable sub-surface doping. Higher energy means more dopant ions penetrate deeper. High energy of ion results in damage to semiconductor crystal

Question 22

Diffusion

Answer 22

Introduce a 100% dopant layer to the surface of a semiconductor region to be doped. Heat treatment promotes diffusion of dopant into semiconductor. Different dopant profiles result from having fixed or unlimited dopant source from the temperature and from anneal time. Multiple doping operations can be used to create alternating electronic character through the device depth

Question 23

How are patterns made on semiconductor?

Answer 23

Defined using an electron or photo-sensitive resist and irradiating with focussed electrons or light of a suitable wavelength

Question 24

Patterning by electron-beam lithography

Answer 24

Typical resist PMMA. Deposit resist layer. Write in pattern with electron beam (5-100keV) which breaks the polymer chains and increases solubility. Dissolve plastic regions exposed to electron beam. Deposited final material. Lift off resist in acetone to leave desired structure

Question 25

Patterning using photolithography

Answer 25

Deposit resist layer expose to extreme ultraviolet radiation through optical mask (smaller features need smaller wavelength). Dissolve resist regions exposed to electron beam. Deposit final material over all. Lift of resist in acetone to leave desired structure e

Question 26

Etch process for patterning

Answer 26

Deposit material layer (semiconductor) on substrate. Add pattern of resist. Etch away exposed semiconductor with ions/chemicals. Remove resist chemically