ENCE260 Flashcards
(107 cards)
1
Q
CPU to Internal peripherals
A
control bus, data bus (double)
2
Q
CPU to memory
A
control bus, address bus, data bus (double)
3
Q
CPU key functions
A
arithmetic,
evaluate logic expressions,
determine and control program flow
4
Q
expression for number of combinations in a sequence
A
M^n
M = number of combinations
n = number of digits
5
Q
Word length
A
default number of bits manipulated by microcontroller
ATMega32u2 is 8bit
6
Q
Two’s compliment
A
swap the bits and add 1
1 more negative than positive
eg: 111 is -1,
000 is always 000.
7
Q
Floating point
A
31st bit MSB
S-E8-F23
1 = -, 0 = +, same as two’s
write the number as binary, keeping the dot
E = Add 127 to amount you moved dot
F = fractional - 2nds, 4ths, 8ths, 16ths, etc
8
Q
Combinational logic
A
output is a function of input only
9
Q
Sequential logic
A
combinational logic with memory
10
Q
SR latch
A
2 Nor gates
R sets one Q to on and one to off, which stays,
S switches it and stays
Issues - don’t know what initial state will be
##########
11
Q
D flip flop
A
SR latch that works with a clock signal
basically just add an and for data and clock (to S)
and a not with the other and (for R)
12
Q
Register
A
D flip flops that share a clock signal and output to a data bus
13
Q
Data bus
A
width equal to CPU word length
transports data to and from CPU
14
Q
Address bus
A
specifies memory locations
address space is 2^buswidth
controlled by CPU
16 bit in ATMega32u2
15
Q
Control bus
A
sends commands to hardware from the CPU
16
Q
Von-Neumann/Princeton architecture
A
all memory is stored in one place. Loses efficiency, as you can process only one thing at once instead of 2
17
Q
Harvard architecture
A
instruction and data memory separate
18
Q
canonical form logical functions
A
logic functions made of just the three fundamental functions:
AND, OR, NOT
19
Q
algebraic properties: closure
A
if a,b elements of B, any function involving a and b will be an element of B
20
Q
algebraic properties: identity
A
a.1 = a, a+0 = a
21
Q
algebraic properties: annihilation
A
a.0 = 0, a+1 = 1
22
Q
algebraic properties: absorption
A
a+(a.b) = a
a.(a+b) = a
23
Q
algebraic properties: Idempotence
A
a+a = a, a.a = a
24
Q
algebraic properties: or-compliment
A
a+!a = 1
25
algebraic properties: and compliment
a.!a = 0
26
algebraic properties: De Morgan's
!(a+b) = !a.!b
!(a.b) = !a+!b
27
Make the 3 fundamental functions out of NAND gates
!a = !(a.a)
a.a = !(!(a.a).!(a.a))
a+b = !(!a.!b)
28
minterm
the output of karnaugh maps
and of either notted or not notted variables, must have each variable present. combine these by cancelling individual notted and not notted variables
29
Karnaugh maps
used for logic circuit design.
rectangles must be 2^n by 2^m
30
sum of products SOP
summation of the minterms of a truth table
31
General purpose registers
IO register for ALU - increases speed - 32 registers in ATMega32u2
32
special/control registers
stores special variables that control overall behaviour
33
PC
program counter, part of the special/control registers.
stores address of the next instruction in program memory, controls/sets program flow
34
SP
stack pointer, part of the special/control registers.
35
Control/execute unit
- fetches instructions from memory to the instruction register
- decodes opcode
- loads variables into GPR/SR and then controls loading them into the ALU.
- Instructs the ALU what operations to execute and when.
- stores output of the ALU into the correct GPR
36
Half adder
built from a left-right separation of a+b truth table
C - AND
S - XOR
37
full adder
two half adders combined.
The carry bits get ORed and outputted along with the sum. This makes the sum the 1's column and the Carry the 2's column
38
Decoder/Encoder
turns the bus' n traces into 2^n outputs (decoder) and vice versa
works by breaking input into two traces, one with a not.
00 0001
01 0010
10 0100
11 1000
39
Priority encoder
only takes the highest 1 from the input
40
Multiplexer/demultiplexer
S chooses whether I0 or I1 is outputted (2:1 mux)
S needs to be sufficiently large to account for as many input options there are. generally 2^n = i
41
full adder subtraction
Goal is two's compliment. Done by XOR with input line and a Sub line. The sub line goes in to the first carry to count as +1
You can use a truth table to confirm.
42
shift register
D flip-flops in series(Q -> D) with a common clock
Because change only occurs on the rising edge, the shift has to propagate through n rising edges before it stops
43
Ripple counter/timer
shift register where each !Q is connected back to D.
When rising edge detected, !Q goes high until another rising edge is detected. This doubles the time it takes to change for each flip flop along the register. When you take the output of this register, it appears to be counting up by 1 each rising clock edge.
note: count down by taking Q (instead of !Q) and applying XOR between the flip flops.
44
propagation delay calculating
put n NOTs before an AND for one of the inputs. The resulting pulse of 1 will be n * propagation delay.
45
Synchronous counter
built from ripple counter.
uses a common clock.
truth table for count states and next states shows what combinational logic needs adding.
Q0 -> !Q0 handled by !Q---D
Q1 -> Q1 XOR Q0
Q2 -> Q2 XOR (Q1.Q0)
all fed into respective D inputs.
46
Finite state machine
initial state
inputs
transitions
outputs
47
Moore FSM
Combinational logic based on input and current states determines states.
Feeds to combinational logic that performs tasks without further input
48
Mealy FSM
Moore FSM with inputs also fed to the functional combinational logic
49
tristate buffer
electronically controlled switch that boosts the power
50
PINx output (GPIO)
Activated from the data bus going into the DDxn flip flop (set to 1). output is a tristate buffer (and pull-up resistor) control line that drives the PORTxn flip flop value to the pin
51
PINx input (GPIO)
runs through a digitiser and sleep controller, then the PINxn register gets pushed by a tristate buffer to the data bus
52
Pull-up resistor
only on when DDxn output is 0 (input state) and PORTxn output is 1 (active state).
Pulls up to high voltage to avoid floating pins. When the pin is grounded, current bypasses pin and input is 0. The resistor protects from the high voltage causing short circuit.
53
MOSFET
Useful for controlling circuits with high voltages. The voltage runs perpendicular to the IO pin controlling it. Used in pull-up resistors.
54
Watchdog timer
counts down and resets microcontroller if it reaches 0. Prevents loops.
Needs to be set to top periodically.
55
ATMega32u2 timer functions
prescaler
capture
compare
PWM
56
OCRnx
output compare register
n is the timer, 0 for 8bit, 1 for 16 bit.
x is the instance of the register (there are 3: A,B,C)
A defines the top point, the point where - when comparison matched - the counter counts down
57
TCNTn
Timer counter
0 - 8bit
1 - 16bit
58
OC.nx
Output channel for PWM (to pin)
based on duty cycle
n - TCNTn
x - instance of OCRnx
59
PWM period
2*OCRnA/fclk
60
duty cycle
% of time OC.nx is 1
OCRnx/OCRnA
61
ADC
analogue digital conversion
sampling - discretise time
quantise - discretise voltage
encoding - represent as binary
62
SREG
status register - in special registers
7: I Global interrupt enable/disable
6: T Transfer bit BLD, BST instructions
5: H Half carry flag
4: S N XOR V for signed tests
3: V Two's compliment overflow flag
2: N negative from arithmetic logic
1: Z zero from arithmetic logic operation
0: C carry flag for arithmetic logic
63
X, Y, Z in special registers
indirect address registers
X - 27 and 26
Y - 29 and 28
Z - 31 and 30
Stores addresses in GPR for faster access
64
Opcode
Syntax | Operands | Operation
C registers | Opcode | Flags
adiw Rd+1:Rd, k |dom/range| Rd+1:Rd <- Rd+1:Rd + k
PC <- PC + 1 |Binary w/ vars| S,V,N,Z,C
65
Setting a bit
PORTx|= (1<
66
Clearing a bit
PORTx &= ~(1<
67
Toggling a bit
PORTx ^= (1<
68
test a bit
result = (PORTx & (1<
69
active high/low
on for high/low output voltage, respectively
70
pull down resistor
goes to ground for active high circuits
eliminates floating pin.
71
timer resolution
time between each increment
1/fclk
72
max delay (timer)
T = 2^n * resolution
73
ATMega32u2 prescaler usage
Timer counter control register
TCCR1B
(1 as in TCNT1)
(uses a mux internally, CSn0, CSn1, CSn3)
0: off
1: no prescaling
2: 8
3: 64
4: 256
5: 1024
74
underflow
calculation is too close to 0 to be represented. common with integer division. eg: 10/5x10 (0) is not the same as 10x10/5 (20)
75
LED matrix on/off
MOSFETS are closed when input is low. They have an inverse logic.
Both row and column therefore need to be low for the LEDs to be high->low
76
Navswitch and LED combined functionality
both share the same pin. Because LED is active high and switch is active low, LED is on both when switch is off (pull-up resistor disconnected) and on (switch takes the pin to ground before the LED)
77
paced loop overflow issue
going past the pacer period builds up after each iteration (assuming uniform function time) until there is an overflow of TCNTn itself, causing a really long pacer wait. This misses a whole cycle.
78
Periodic scheduler
CPU sleeps when not time to execute. Paced loop is 100%.
TASK_RATE / x
if a task takes too long, can get timing jitter.
79
task execution rate
for periodic scheduling
sum of function execution times/execution period
80
half duplex
one at a time
81
UART
universal asynchronous receiver/transmitter.
bit by bit.
Tx shift register -> Rx shift register for both. 2 wires.
82
Baud rate
maximum number of bit transitions per second
83
serial data transmission sequence
idle line - high
start bit - low
LSB first
data
parity bit
stop bit
84
Parity bit
makes the whole transmission odd (odd parity bit)
eg: if data has 4 1s, parity will be 1 to make 5 total odd bits.
85
USART registers on ATMega32u2
UCSR1A - control and status register
7: RXCn - receive complete
6: TXCn - Transmit complete - entire register shifted out
5: UDREn - data registry empty
UDR1 - Data register
Baud rate register
86
IR modulation
done to distinguish from ambient light. done only on 0. TCNT0 used. 36khz common.
87
C preprocessor
reads C source file, header files, expands macros. outputs .i
88
C compiler
takes preprocessor output, checks for syntax errors, compiles to assembly. outputs .s
89
C assembler
converts assembly to machine code, stored in binary. outputs .o
90
loader
loads .out executable to .hex on the microcontroller
91
makefile cryptic features
$^ -o $@
all prerequisites -o target - used for .out line
$< is first prerequisite, used for O file lines (first prereq is .C)
92
Make clean
.PHONY: clean
clean:
-$(DEL) *.0 *.out *.hex
93
git commands
add -> commit (-m message "message") -> push (origin main)
<- pull/clone (origin main)
add -> commit
<- checkout HEAD
add
<- checkout
add -> commit
<- diff HEAD ->
add
<- diff ->
HEAD is most recent commit
94
Encapsulation
putting related functions and data structures into its own module
95
header file structure
#ifndef "header_h"
#define "header_h"
#include "other_h"
functions
#endif
96
Waterfall
specifications, design, implement, test/debug, maintenance
97
Types of design methodology
top-down
bottom-up
hybrid
98
coupling (design)
measure of modularity (how separate each module is)
99
cohesion (design)
how related the functions are in each module
100
Address bus width
log2(bits/8*words)
equivalent to
log2(memory byte count)
101
Fetch
read PC from special register,
get function from program memory,
store opcode in instruction register
102
Decode
interpret opcode
set up address busses, control lines (ALU), register address lines, all set up for I/O
103
Execute
ALU performs operation using GPRs as I/O
104
Special registers
Rd: Destination
Rr: Source
R: Result
K: Constant data
k: constant address
b: Bit in I/O register (3 bit)
s: Bit in status register (3 bit)
X,Y,Z: Indirect Address Registers
A: I/O location address
q: Displacement for direct addressing (6-bit)
105
Classes of instruction
Data transfer
Arithmetic/logic
Branching (PC++, +-k)
106
Phony target
107
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