IA: 1P3: Digital Circuits and Information Processing Flashcards

Question

What is the graphical symbol for a XOR gate?

Answer 1

They are usually 2-input

Answer 2

It is a NOT AND gate, it is like having a NOT gate after the output of an AND gate. The output is FALSE if and only if both of the inputs are TRUE

Answer 3

## Footnote Note: the circle on the output of the gate denotes an inverter

Answer 4

It is a NOT OR gate, it is like having a NOT gate on the output of the OR gate. The output is TRUE if and only if both of the inputs are FALSE

Answer 5

## Footnote Note: the circle on the output of the gate denotes an inverter

Answer 6

1. For the resistor: Vᵣ = IR 2. For the "thing": Vₜ = 10 - Vᵣ 3. Plot the line for the resistor on an I-R graph 4. Plot the characteristic of the "thing" but flip it horizontally, with it touching the x-axis at 10V. By doing this you make it so "Vₜ = 10 - Vᵣ" 5. The operating point is where both lines intersect ## Footnote Rule of thumb: Whatever is connected to ground you just plot normally, whatever is connected to the supply rail you flop horizontally

Answer 7

When Vgs reaches a threshold voltage (Vₜ)

Answer 8

You can define voltage levels for the logic variables. For example: * Voltage > 9V is logic 1 * Voltage < 2V is logic 0 The gate will work if: * Vᵢₙ > 9V ⟹ Vₒᵤₜ < 2V * Vᵢₙ < 2V ⟹ Vₒᵤₜ > 9V

Answer 9

A tool used in digital circuits to help track the values of logic variables step by step through the circuit.

Answer 10

When you have to implement a complicated logic function you don't have to design a special transistor circuit to provide the functionality. Instead you just but an integrated circuit (or chip) that provides the appropriate gates

Answer 11

Stray capacitance: The output of each gate is connected by a length of metal track to the input of the next. This has capacitance to ground. Therefore the circuit model is modified by connecting a capacitor between Vₒᵤₜ and ground. This means that each time the input switches, the output does not switch immediately - there is a time delay.

Answer 12

Transistors are far smaller than resistors, therefore by using a FET you save a lot of space on the silicon chip. This allows the logic gate to be about 100x smaller (and cheaper!)

Answer 13

You can make a MOSFET behave (almost) like a resistor by connecting the gate to the drain. Thus Vgs = Vds. This does not create a completely linear line when plotting Ids against Vds, so it will not behave exactly the same as a resistor, however it is fairly close.

Answer 14

Power consumption. NMOS's use resistors/NMOS transistors which dissipate large amounts of energy even when idle. Therefore NMOS circuits consume a lot of energy even when not switching as there is always a current flowing. This leads to a high energy usage and heat generation in larger circuits.

Answer 15

Complementary MOS. CMOS logic uses both NMOSFETS and PMOSFETS. It tackles the issue of power dissipation in NMOS logic.

Answer 16

A PMOSFET is essentially an NMOSFET with all the polarities reversed: ## Footnote Note: The arrow direction on the PMOS (opposite to NMOS)

Answer 17

When Vgs is negative

Answer 18

In a CMOS circuit at a given state, only one of the PMOS and NMOS are ever on at a time - one of them is off at all times. The circuit only draws current momentarily during transitions from one state to another (when both transistors are momentarily on at the same time). Therefore there is no static power dissipation.

Answer 19

* Vgs for the NMOS would be 4V, so you must choose the Vgs = 4V characteristic curve and plot it. * Vgs for the PMOS would be -6V, so you must choose the Vgs = -6V characteristic curve and then **flip it horizontally** (as it is connected to the supply rail) and then plot it

Answer 20

Neither high or low state dissipate power. Power is only dissipated when the states are switched.

Answer 21

* NMOS (N-channel MOSFET) * CMOS (Complementary MOSFET) * TTL (Transistor-Transistor Logic) * ECL (Emitter Coupled Logic)

Answer 22

* Try to minimise the number of gates being used. This can lead to smaller chips and lower costs. * You must also be able to manipulate the expressions to use only gates of certain types if there is a limitation on the types of gates - some gates may be readily available and cheap.

Answer 23

## Footnote Note the bottom one in particular (unique to boolean algebra)

Answer 24

Any valid statement is also valid when: ## Footnote ONLY valid when all 4 of these changes are made simultaneously

Answer 25

Expand each term until it includes one instance of each variable (or its compliment). This may then make it possible to simplify the expression by cancelling terms in the expanded form

Answer 26

In a simple expression you can change all the operators from OR to AND (and vice versa) provided that you put a bar over each term individually and a further bar over the whole expression.

Answer 27

Connect the inputs

Answer 28

Connect the inputs

Answer 29

* Sum of Products (SOP) * Product of Sums (POS) It can be difficult to convert between SOP and POS by algebraic manipulation

Answer 30

It is easiest to write down an expression for what you want directly

Answer 31

It is easiest to write down an expression for the inverse of what you want and then use De Morgan's theorem and an inversion to obtain what you want.

Answer 32

A hardware description language used to describe systems.

Answer 33

**V** = Very high speed integrated circuits **H** = Hardware **D** = Description **L** = Language

Answer 34

* Interface * Architecture Specification

Answer 35

A rectangular array of cells. Each possible state of the input variables corresponds uniquelt to one of the cells, and in the cell we write the corresponding output state. They are a powerful visual tool for carrying out simplification and manipulation of logic expressions with up to 5 input variables

Answer 36

**The pattern of high and low inputs.** i.e. 00, 01, 11, 10

Answer 37

* Write down the simplest sum-of-products expression for the output from the Karnaugh map * Use De Morgans theorem to convert this to an expression using NAND gates

Answer 38

* Use the Karnaugh map to write down the simplest sum-of-products expression for the inverse of the output. This involves finding terms to cover the blanks between the boxes filled with ones * Use De Morgan's theorem to convert this to an expression using NOR gates.

Answer 39

Map the opposite way and then use a final inverter gate to change the output back again.

Answer 40

No they can be used for up to 5 input variables

Answer 41

For some output states, a certain combination of input variables may not matter. These are known as "Don't care states" and are marked with an **X** on the Karnaugh map. They can be chosedn to be 0 or 1, whichever helps to produce the simplest logic.

Answer 42

A static hazard is when a signal undergoes a momentary transition when it is supposed to remain unchanged.

Answer 43

A dynamic hazard is when a signla changes more than once when it supposed to change just once.

Answer 44

Fix a static 1-hazard by drawing the Karnaugh map of the output concerned. Make sure all the sum-of-products terms overlap.

Answer 45

Fix a static 0-hazard by drawing the Karnaugh map of the inverse of the output concerned. Make sure all the sum-of-products terms representing the inverse overlap.

Answer 46

Fix dynamic hazards by redesigning the circuit to simplify the logic

Answer 47

A type of binary code in which only one bit changes between two successive values

Answer 48

As you move from a cell to its neighbour in a Karnaugh map only one variable changes. Because the map wraps round this is also true when moving from top to bottom and from far left to far right. This property can be used to produce a code in which only one bit changes at a time.5

Answer 49

A binary numbering system where two consecutive values differ by only one bit (a type of unit distance code).

Answer 50

In regular binary counting (e.g. 0111 to 1000), multiple bits can change at once. If a signal is delayed or misread during a transition, it can cause a hazard (e.g. between 0111 and 1000 the output may momentarily be 1111). By using a unit distance code the chance of these hazards occuring is reduced.

Answer 51

* Binary - base 2 * Octal - base 8 * Decimal - base 10 * Hexadecimal - base 16

Answer 52

Binary is base 2. Each digit is either 1 or 0.

Answer 53

A binary digit

Answer 54

a storage location for an 8 bit binary number

Answer 55

8 bits (one byte)

Answer 56

* **Unsigned byte** (positive numbers only): It can store numbers from **0 to 255** (2⁸ - 1) * **Signed byte** (can store positive and negative numbers): It can store numbers from **-128 to +127**.

Answer 57

It’s the leftmost bit in a binary number. It holds the highest place value.

Answer 58

It's the rightmost bit in a binary number. It holds the lowest place value.

Answer 59

Use the remainders from successive division by 2. Read upwards from MSB to LSB.

Answer 60

Octal is base 8. Each digit can be one of 8 numbers, 0-7.

Answer 61

Use the remainders from successive division by 8. Read upwards from MSB to LSB.

Answer 62

Divide the binary number into 3-bit groups and work out the octal digit to represent each group.

Answer 63

Hexadecimal is base 16. Each digit can be one of 16 **symbols**, 0-9 and then special symbols for 10-15.

Answer 64

* 59**₁₆** * 59**ₕ** * **$**59 * **0x**59

Answer 65

Use successive division by 16, reading the remainders upwards from MSB to LSB

Answer 66

Divide the binary number into **four-bit groups** and work out the hex digit to represent each group.

Answer 67

We use a strategy called 2's complement. In this form: * The MSB for all positive numbers is zero * The MSB for all negative numbers is 1

Answer 68

Look at the first digit of the binary number: * If this is zero, then it is a positive number. In this case you can read it off/convert it to decimal as you would an unsigned binary number. * If this is one, then it is a negative number. In this case you must first reverse the 2's complement. To do this you must invert all the bits and then add 1. Read this off like a normal binary number - this is the magnitude of the number. The final number is the the negative of the magnitude.

Answer 69

Invert all the bits and then add one.

Answer 70

When adding 2 signed 8 bit binary numbers (in 2's complement form), we can use normal binary addition. For subtraction we simply add the 2's complement negative version of the number. * Perform the addition as usual * Ignore the carry out of the 8th bit (carry bit) - we are only concerned with 8 bits. * The result should be interpreted as a signed 8-bit number (-128 to 127)

Answer 71

* **For unsigned binary arithmetic**: If the carry bit is 1, then there was a carry out from the MSB. Therefore if the carry bit is 1 then there has been an overflow. * **For signed binary arithmetic**: Overflow occurs if the carry into the MSB ≠ carry out of the MSB.

Answer 72

The MSB indicates the sign (0 ⟹ +, 1 ⟹ -). The remaining 7 bits contain the magnitude. It is not commonly used as: * We will have 2 0's (-0 and +0) * Separate circuits are required to add and subtract numbers

Answer 73

**BCD is when each decimal bit is coded into a 4-bit group.** It is not an efficient way of storing numbers, but is easy to code and decode.

Answer 74

Alphanumeric character codes are numeric representations of letters (A-Z, a-z), digits (0-9), and sometimes symbols that are used by computers to store and process text. Examples include ASCII and Unicode.

Answer 75

It is the "American Standard Code for Information Interchange". It is a very commonly used Alphanumeric Character Code system. The standard version is a 7 bit code with the remaining but set to zero or used for parity. It includes 32 "control codes". The rest of the numbers are for lower case letters, upper case letters, numbers, and punctuation. The extended version of ASCII uses all 8 bits to provide 128 additional graphics characters.

Answer 76

It is a 16 bit alphanumeric character code system. It includes all the same features as extended ASCII but also Covers ALL characters in every language, emojis, and mathematical symbols.

Answer 77

Parity is the simplest method for error detection coding when transferring binary data through an imperfect data channel. A parity bit is added as to ensure there is always an even number of 1's in the byte. If the byte has an odd number of 1s the parity bit is set to 1 to make it even, and if the byte has an even number of 1s the parity bit is set to 0 so that there are still an even number of 1s. Once the byte has been transferred through the channel, we count the number of bits that are on in each number, accepting any that have an even number and rejecting any that have an odd number. This allows you to detect 1-bit errors.

Answer 78

It can only detect 1-bit errors, more serious errors may go undetected

Answer 79

A bistable

Answer 80

A circuit which has 2 stable internal states and can remain in either state indefinitely until an external input causes it to switch to the other state.

Answer 81

* We start with the set-reset (SR) bistable * A gated-SR bistable is built using an SR bistable * A master-slave bistable is built using two gated-SR bistables * A D-type latch is built from a master-slave bistable * A JK bistable is built from a master-slave bistable

Answer 82

**Inputs:** S (Set), R (Reset) **Outputs:** Q1 and Q2 **Behaviour:** * S = 1, R = 0: Sets Q1 = 1, Q2 = 0 * S = 0, R = 1: Resets Q1 = 0, Q2 = 1 * S = R = 0: Retains previous state (memory) * S = R = 1: Invalid condition **Operation:** * S will turn Q₁ on and Q₂ off. They will stay at this state even if S is turned off. * Until R turns on (RESET event, Q₁ = 0 Q₂ = 1) * R turns Q₂ on and Q₁ off. They will stay at this state even if R turns off. * Until S turns on (SET event, Q₁ = 1 Q₂ = 0) We therefore have memory. The circuit state depends not onlt on the current values of S and R but also on their values in the past.

Answer 83

The complete operation of the bistable can be described using the below state diagram: ## Footnote **Note: S = R = 1 is not allowed, it is invalid**

Answer 84

When mechanical switches are pressed they can bounce causing brief, unintended on/off pulses. Unless debounced, when you click a switch once it may be read as many presses due to bouncing. This can be seen in the graphs for A and B below. Contact debouncing is the process of removing these unwanted bounces, ensuring a clean digital transition. This can be achieved by using an SR bistable, when the switch is pressed it will set/reset the bistable placing it in one of its 2 stable states. Because an SR bistable retains its state until explicitly changed, it ignores the rapid fluctuations caused by bouncing. The output remains steady, switching only when the switch is intentionally pressed again to trigger the opposite state.

Answer 85

It is the same as an SR bistable, however it introduces a gate signal (G) which only allows the bistable to change state when G is high (due to the AND gate). This can be used for synchronous control of state changes as the gate signal could be set to a clock. This would allow for accurate timing of output changes for corresponding SR inputs.

Answer 86

A Master-Slave bistable is composed of two gated SR bistables. **The outputs of a Master-Slave bistable are always logical opposites.**

Answer 87

The output of one of the gated SR bistables is connected as the input to the second gated SR bistable (Q1 to S and Q2 to R). A clock is passed directly to the second bistable and is passed through a NOT gate to the first bistable. Therefore: **When the clock is low:** The first (master) is sensitive to input signals **When the clock rises:** The second (slave) is sensitive to its inputs i.e. the outputs of the first bistable This ensures changes only occur on a clock input **The outputs of a Master-Slave bistable are always logical opposites.**

Answer 88

Asynchronous inputs can be used for immediate state control - independent of the clock * S&R are both gated. The inputs are both dependent on the clock signal - synchronous to CLK * **PR** and **CLR** are not gated - asynchronous They are active low: * When PRESET is low, Q goes high and Q *bar* goes low * When CLEAR goes low, Q *bar* goes high and Q goes low

Answer 89

Input data replaces S and R in a master-slave bistable. On the clock edge (as the clock goes high) the output (Q) gains the value of D. It is useful for retrievel of signals. ## Footnote The illegal state of S = R = 1 is eliminated by forcing S = not R. Thus a single "input data" replaces both

Answer 90

A JK bistable is a type of edge-triggered flip-flop that is a refined version of the SR bistable, designed to avoid the invalid state of S = R = 1. The case of the inputs (J and K) both being 1 is now a useful input.

Answer 91

* Start with a simple SR bistable * Add gate input: bistable can only change state when the gate is high * Put two SR bistables together: create master-slave bistable. Output only changes when clock input rises (positively edge triggered) * Add asynchronous inputs: preset and clear * **Add AND gates to prevent S = R = 1 at input to first SR bistable** of master-slave pair. The inputs to these 2 AND gates are J and output *bar* and K and the output. Create JK bistable.

Answer 92

* J = K = 0 → No change * J = 0, K = 1 → Q = 0 (like RESET) * J = 1, K = 0 → Q = 1 (like SET) * J = K = 1 → Toggle

Answer 93

The JK bistable will remain in the state determined by the J and K inputs, changing only on a rising clock edge, until altered by the asynchronous inputs. The JK bistable will then immediately take the state set by the asynchronous inputs until the next clock pulse where it will return to the state set by the J and K inputs. (In the case of J = K = 1 [toggle], the bistable will invert its current state - which means it will become the opposite of the state forced by the asynchronous input).

Answer 94

The characteristic/excitation table defines what inputs are required to achieve a particular output change:

Answer 95

They can be classified into 2 groups: * Counter circuits: Divide by n counters, ripple counters, synchronous counter, Johnson counter * Memory circuits: shfit register, parallel loading shift register

Answer 96

It consists of a single JK bistable with J = K = 1

Answer 97

It is a single JK bistable with J = K = 1, therefore toggles every rising clock edge. This leads to an output where the frequency is half of the input clock. There is a propoagation delay.

Answer 98

The small amount of time taken for the bistable to change its state based on the inputs when the clock goes high.

Answer 99

It is a chain of JK bistables where the output *bar* of each stage acts as the clock for the following stage.

Answer 100

As each output*bar* acts as a clock for the following stage, it divides the frequency exponentially. In the below example there are 4 bistables, so it is a divide by 2⁴ = 16 counter. As it is the output ***bar***, each stage acts on the falling edge of the previous stage (rather than the usual rising edge). However, due to propagation delays accumulating, glitches/transitory states can occur.

Answer 101

Transitory states: * Transitory states are glitches due to finite delays between clock signals changing and the JK output changing * This can arise if we use the output of a bistable as the clock to another bistable

Answer 102

It is similar to a ripple counter, however all bistables share a common clock so there is no propagation delay accumulation and all outputs change simultaneously.

Answer 103

As the inverted output (Q bar) is used as a clock for the following stage. Therefore the rising edge of Q bar drives the following stage - but the rising edge of Q bar, is the falling edge of Q.

Answer 104

* All bistables share a common clock so there is no propagation delay accumulation and all outputs change simultaneously. * The output of a JK bistable is high when the clock is high and the output of the previous 2 bistables is 1

Answer 105

* A shift register is a series of D-latches with the output of one bistable being the input to the next. They are all connected to a common clock. * A shift register takes in data, stores it, and shifts it through a chain of bistables. **The data is shifted one position per clock pulse.**

Answer 106

Parallel loading allows the initialisation of a shift register with parallel data. It allows a shift register to take in multiple data bits simultaneously - with one input needed per bit - and store them in its bistables in a single clock cycle. For each following clock cycle the bits are shifted along the bistables.

Answer 107

A parallel loading shift register is used to send one data bit at a time across the serial link to another shift register. It’s the opposite of a parallel data link. You can clock the data through and then (when all the data is in position) read it in one go. As it is a single wire, far fewer wires are required than for a fully parallel link, however it is much slower as data is sent one bit at a time.

Answer 108

A Johnson counter uses a shift register of length N to produce a sequence of length 2N. The output of the last bistable is inverted and fed to the first. As seen in the diagram below, each bit is shifted one along, whilst the bit of the final bistable is shifted AND inverted.

Answer 109

A Johnson counter

Answer 110

This design is vulnerable to glitches, if 101 is detected an asynchronous clear must be performed to reset the bistable and restart. The counter resets to 000 - giving a 5-state cycle: 000 → 001 → 010 → 011 → 100 → (reset) ## Footnote FLASHCARD INCOMPLETE, RESEARCH THIS

Answer 111

1. State diagram 2. Bistable allocation 3. State transition table 4. Karnaugh maps 5. Circuit diagram

Answer 112

Number of JK bistables = log₂(number of states) ## Footnote you must round up!

Answer 113

It is the first stage in synchronous logic design, it defines all the distinct states of the system and how they transition based on inputs: * It has a box for each of the required states * For each of the boxes (states) arrows representing each of the possible combinations of the inputs point to the resulting state if these were the inputs when the circuit was in this state (this can be the next state, a previous state, or even itself) There must be a path leaving each state for every possible combination of inputs (i.e. for a case of a 2 input system, there must be 4 paths leaving every state)

Answer 114

It is the second stage in synchronous logic design: Assign binary codes to represent each state you can choose from which bistable outputs (or combination of) that each digit will be taken from. For N states, you require log₂(N) JK bistables (rounded up to the nearest integer) ## Footnote A key aspect of this is that you decide the binary codes chosen to represent each state!!!

Answer 115

It is the third stage in synchronous logic design: Create a table showing the current state, the inputs, the corresponding next state for the input and current state, and then the required bistable input values to make the transition. You can determine this using the excitation table in the data book. Using the excitation table in the databook, you can compare Qₙ and Qₙ₊₁ and hence determine the required J and K values. For the below example this should be done for both bistables A and B ## Footnote Note: You should handle unused states (i.e. if you somehow end up in an intended unused state you should be returned to the initial state)

Answer 116

Karnaugh maps are the fourth stage of synchronous logic design: Use Karnaugh maps to determine the simplest Boolean logic expressions for each bistable input (i.e. each J and each K for every bistable)

Answer 117

This is the fifth and final stage of synchronous logic design: Based on the Boolean logic expression obtained from the karnaugh maps construct a full logic circuit. Note: all bistables should be clocked synchronously (together)

Answer 118

A weighted resistor DAC (Digital-to-Analog Converter) is a circuit that converts a binary number (digital input) into a corresponding analog voltage using resistors with values weighted according to binary significance.

Answer 119

* Lots of resistance values whicha re difficult to implement * If the LSB is 5% accurate then the MSB must be 5%/2ⁿ⁻¹. If n=8 this comes to 0.04% which is time consuming and expensive to achieve * A wide range of resistor calues are required. These will need to be made from different materials so the way they change with temperature will be different. The output of the circuit will probably drift as it warms up

Answer 120

A type of digital-to-analog converter that uses only two resistor values -R and 2R - arranged in a repeating ladder-like network to convert a binary digital signal into an analogue voltage

Answer 121

Each stage halves the current so binary weighting is maintained

Answer 122

R-2R resistors are: * Much more accurate * Potentially cheaper * More stable and scaleable

Answer 123

Vₒᵤₜ = Gain x (Vᵣₑ𝒻 - Vᵢₙ), but when the gain is very large: Vᵢₙ > Vᵣₑ𝒻 → Vₒᵤₜ = V- Vᵢₙ < Vᵣₑ𝒻 → Vₒᵤₜ = V+ The output switches depending on whether Vin or Vref are greater

Answer 124

It is like a 1 bit ADC comparator but it adds positive feedback to create a hysteresis effect

Answer 125

Unlike the 1 bit ADC comparator, it has two thresholds: upper and lower, to avoid false triggering due to noise. * If Vin is low intitially, then Vin must rise above Vupper for Vout = 0 * Then Vin must drop below Vlower for Vout = 1

Answer 126

A flash ADC uses a resistor ladder and many comparators. Each comparator compares Vin to a different reference level and it outputs a parallel binary output

Answer 127

Lots of comparators required: * 8-bit resolution needs 256 comparators, 12-bit requires 4096!

Answer 128

* Alternative to flash ADC: much slower, but uses only one comparator. * A DAC generates a ramp (or staircase) signal. * When DAC output drops below Vin the counter value is the digital output

Answer 129

It takes 2 bits Aᵢ, Bᵢ, and carry in Cᵢ, outputs sum Sᵢ and carry out Cᵢ₊₁ * Carry bit: Needs 2 or more bits to be HIGH * Sum: Needs and odd number of inputs to be HIGH

Answer 130

* Combines multiple full adders to add multi-bit numbers. * Carry-out from one adder feeds into carry-in of the next

Answer 131

If A is inverted and carry in C₀ = 1, then the adder performs subtraction: S = B - A

Answer 132

* A microprocessor is a computer on a chip, it is used to control digital devices. * They run programs made of simple, low-level instructions

Answer 133

the foundational design for most modern general-purpose computers

Answer 134

The **microprocessor** itself comprising:: * An **Arithmetic Logic Unit (ALU)** which performs mathematical and logical operations * A **control unit** that manages the execution of the code / instructions * Multiple **registers** that are used as **temporary** storage for instructions and data **Input** and **Output** ports to interface to the outside world **Buses** to connect everything: * **Address bus** to address the memory locations and i/p and o/p ports * **Data bus** to carry data to/from locations (bidirectional) * **Control bus** to send control signals

Answer 135

* Performs operations like addition, subtraction, AND, OR, etc * Can perform simple comparison operations * To make an n-bit ALU, cyou must connect n one-bit ALU's together using a bus

Answer 136

* The data bus is bidirectional * The address and control busses are unidirectional ## Footnote Modern processors may use 32-64 bit buses byt the basic architechture remains

Answer 137

* Address (of the memory location) is set on the address bus * Set the read wire of the control bus to **high** * Set the address valid control wire high These will come together the activate the memory chip select (active low) Contents of the memory location are placed on the data bus and retrieved Once the data is read (usually into a register on the microprocessor), the control wires can be "reset"

Answer 138

* Address (of the memory location) is set on the address bus * Set the read wire of the control bus to **low** (this requests a write operation) * Set the address valid control wire high Contents of the data bus is then placed at the memory location Once the data is written to the memory, the control wires can be "reset"

Answer 139

**Total addressable memory locations = 2ᵃ x b** a = number of address wires b = number of data wires

Answer 140

Temporary storage for instructions and data within the microprocessor

Answer 141

A program counter (PC) is a (13 bit for PIC) register inside the microprocessor that stores the program memory address of the next instruction to be executed

Answer 142

The standard instruction cycle for a microprocessor: * The processor first fetches the instruction from the address strored in the PC * The fetched instruction is then decoded so that it can be interpreted by the microprocessor * Once, decoded, the instruction is executed and the PC incremented so that it contains the address of the next instruction

Answer 143

**NO**, they are all in the databook!!!

Answer 144

A digital component that acts like a switch, allowing a signal to pass through when enabled or effectively disconnecting the output when disabled by acting as a very-high impedance

Answer 145

Using MSB address lines to select chips; lower bits select location within chip.

Answer 146

They are treated as memory locations

Answer 147

An assembler translates an assembly language program into op-codes that are understood by the microprocessor

Answer 148

They work bitwise. This means each bit of the operands is independently affected by the operation

Answer 149

General Purpose Input/Output register: For the PIC12F675 the GPIO register acts as a 6 bit wide bidirectional port * All bits but one can act either as an input and an output * The exception is bit 3 which can only be an input

Answer 150

The corresponding data direction for the GPIO is managed by the TRISIO register: * Setting a bit (=1) in the TRISIO register makes the corresponding bit in the GPIO an input * Clearing a bit (=0) in the TRISIO register makes the corresponding bit in the GPIO an output (Note: TRISIO bit 3 is always set)

Answer 151

Several individual bits (flags) in the STATUS register hold information about the result of the last arithmetic/logical operations. These can be used to determine the result of a conditional instruction. Its register locations is 0x03

Answer 152

The carry (C) flag is set when there is a carry from the most significant bit during a calculation. It is bit 0 of the STATUS register.

Answer 153

The zero (Z) flag is set when the result of an instruction is zero. It is bit 2 of the STATUS register.

Answer 154

A byte made up of 2 "nibbles" - each of 4 bits. The DC flag is set whenever this is a carry from the lower to the upper nibble (i.e. bit 3 to bit 4). It is bit 1 of the STATUS register

Answer 155

Flowcharts are a graphical technique for designing short programs: * They encourage design of the overall algorithm * Independent of microprocessor architecture or instruction set * Easier to read than machine code / assembly language

Answer 156

goto makes the program jump to a label. This can be used to repeat loops until a condition is met

Answer 157

For most PIC processors each intruction takes one internal clock cycle to execute. However there are 2 main exceptions: * Instructions (such as goto, call, return etc) which need to replace the PC contents take two cycles * Test/conditional branch instructions: If the conditional branch does not skip the next instruction, only one cycle. If the conditional branch does skip, it discards the next instruction and executes a nop. Therefore there are 2 cycles.

Answer 158

It is used for indirect addressing If a file register address is loaded into FSR, the contents of that register can be read through the Indirect File Register (INDF) This method can be used to access a set of data in memory locations by reading/writing the data via INDF and selecting the next location by incrementing FSR Particularly useful for storing a sequence of data that has been read in through a port

Answer 159

It is automatically used for sub-routines. There is no need to worry about it in the course of day-to-day PIC programming

Answer 160

Subroutines are used to carry out discrete programma functions (or mini-programmes). They allow programmes to be written in manageable self contained blocks which can be executed as required. **call** is used to jump to a sub-routine and **return** to terminate it and return to the main program. **retlw** is similar to return but also stores literal value in W The call instruction has teh address of the sub-routine as an argument

IA: 1P3: Digital Circuits and Information Processing Flashcards

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