interview 2

Question 2

What does stability mean in SRAM cells?

Answer 2

It’s the ability of the cell to hold or switch state reliably under voltage, temperature, and process variation.

Related concepts include Static Noise Margin (SNM), transistor sizing, V_th variation, noise sensitivity, and failure modes such as Read upset, Write fail, and Hold fail.

Question 3

How does voltage affect logic behavior?

Answer 3

Voltage impacts switching speed, leakage current, and noise immunity. At low voltage, circuits become slower and less robust.

Key formulas include Delay ∝ V / (V - V_th)² and Leakage ∝ exp(-V_th / n·V_T).

Question 4

How do you detect marginal SRAM cells?

Answer 4

By sweeping voltage and tracking failure patterns. Automation detects correlations with specific PVT combinations.

Important concepts include voltage-dependent bitflips and statistical variation of bitcells across arrays.

Question 5

What’s your biggest technical achievement?

Answer 5

I improved SRAM yield by automating early detection of Vmin-related instability. This significantly reduced debug cycles.

This involves understanding weak bitcells under process and voltage stress and automating correlation of failures to physical root causes.