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CE161 - Digital Systems Architecture > L8 - Memory > Flashcards

Flashcards in L8 - Memory Deck (30)
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1
Q

What is the name of the memory internal to the processor?

A

Registers

2
Q

How is external memory accessible by the processor?

A

Through IO modules

3
Q

Cache is a form of ______ memory.

a) internal
b) external

A

a) internal

4
Q

In what unit is memory capacity usually expressed

A

Bytes

5
Q

What are the four methods of accessing units of data?

A

Sequential access

Direct access

Random access

Associative access

6
Q

Define “associative access”

A

Word is retrieved based on a portion of its own contents rather than its address

Each location has its own address

Constant retrieval time

Cache memory may use associative

Information can be searched by type

***SPECIAL CASE OF RANDOM ACCESS***

7
Q

Define “random access”

A

Each location has unique, wired in address

Any location can be selected and accessed

Access time is constant - same for any location

Order unimportant

Example: Main memory, cache

8
Q

Define “direct access”

A

Shared read-write mechanism

Individual blocks have unique physical address

Access time depends on physical position of data

Example: Harddrive (R/W Mechanism is the magnetic head)

9
Q

Define “sequential access”

A

Memory organized into units of data calld records

Access is made linearly, i.e. one record after another

Access time depends on position of required data

Example: Tape reel

10
Q

What are the three performance parameters use with regard to memory?

A

Access time (latency)

Memory cycle time

Transfer rate

11
Q

What is the access time (latency) of a memory system?

A

For random-access - time taken for a read/write operation

For non-random-access memory - time taken to position the read/write mechanism at desired location

12
Q

Define “memory cycle time”

A

Access time plus any additional time before another access can commence

Example: time for R/W Head to move back to default position or time for SSD to calculate the address/difference etc.

Concerned with system bus, not processor

13
Q

Define “transfer rate” as it applies to memory systems.

A

Rate at which data can be transferred into or out of a memory unit

For random access memory, 1/(cycle time)

14
Q

What is memory hierarchy?

A

Balance of cost, speed and capacity

In general, increased speed = increased cost & decreased capacity

increased capacity = decreased speed & increased price

etc.

So for a good balance can use many different memory components

15
Q

Describe the process of reading from memory

A

1) Source address put in Memory Address Register
2) Address bus set to value of MAR
3) Control line set to “read”
4) Data bus set to value at address in MAR
5) Memory buffer register set to value of Data bus

16
Q

Describe the process of writing to memory

A

1) Destination address put in Memory address register
2) Data to be written put in Memory buffer register
3) Address bus set to value of MAR
4) Control line set to indicate write operation
5) Data bus set to contents of MBR
6) Data at address in Address bus set to value of MBR

17
Q

Cache memory is a very common modification to what?

A

Von Neumann Machine

18
Q

Why is cache memory used?

A

Faster memory access because reads/writes are cached and cache memory is very fast

19
Q

Describe the cache read operation

A

Receive Read Address from CPU

If block containing address present in cache, fetch and return it from the cache

Otherwise, fetch from the external memory and then store in the cache, using a replacement algorithm if not enough space

20
Q

What are the three most common replacement algorithms

A

Least recently used - most effective; replace the block that was least recently used; most popular option

First-in-first-out - replace block that has been cached the longest

Least frequently used - replace block that has experienced fewest writes

21
Q

What are the two write cycle schemes using the cache?

A

Write through - all write operations also write to the cache; bit pointless to have a cache in this case

Write back - minimises memory writes, updates only made in cache, then at some point all the blocks from the cache are written to the main memory

22
Q

How do hard disks store data?

A

Magnetic substrate which can store a magnetic state indefinitely

23
Q

What is the read/write head in a HDD made of?

A

Crystal.

24
Q

How and why does sectore size change between tracks in a HDD?

A

Outermost tracks have larger sectors

25
Q

What is Rotational Delay in HDDs?

A

Delay while the head finds the right sector

26
Q

What is seek time in HDDs?

A

Time taken to position head at tracks

Mean seek time is 1/3*time from outermost to innermost track

27
Q

What is the access time of a HDD?

A

Sum of seek time and rotational delay

Time it takes to get into position to read or write

28
Q

How do you calculate the average rotational latency of a HDD?

A

Time taken for disk to rotate 180 degrees

29
Q

Why is rotational speed an issue with cds?

A

Data density same everywhere so must spin slower at edge of disc to maintain same data rate

30
Q
A