Lecture 4 - Caches and virtual memory

Question 1

What are three types of cache organization

Answer 1

Direct mapped
Fully associative
n-Way set assosiative

Question 2

What is a direct mapped cache?

Answer 2

A block can be placed only by one location in the cache

Question 3

What is a fully associated cache?

Answer 3

A block can be placed anywhere in the cache

Question 4

What is a n-way set associative cache?

Answer 4

A block can be placed at one of n locations in the cache

Question 5

Compare how cache lines are accessed in the different types of caches

Answer 5

In direct mapped caches, the block is directly gone to. If the data is not there, the address has not be stored in cache

In fully associative caches, the whole cache must be looked through to know if an address is stored in cache.

In set-associative caches, n cache lines must be looked through to know if an address has been stored to cache.

Question 6

What is a problem with direct mapped caches?

Answer 6

Can cause a lot of cache misses, when addresses accessed all translates to the same cache line. This causes one cache line to be switched out on every access, though the rest of the cache is empty.

Question 7

How are bits used in fully associative caches?

Answer 7

tag + byte offset

As addresses can be stored anywhere, no bits are used to find cache clock.

Index bit from direct mapped becomes part of tag in fully associative.

Question 8

What are some problems with fully associative caches?

Answer 8

Because an address can be mapped anywhere, searching for a matching tag can be anywhere.

Question 9

How are n-way set associative caches organized?

Answer 9

Bundle multiple blocks together into sets containing n blocks.

index bits maps to a set

Within the set, do tag-comparison to see if address is stored in cache.

Question 10

What is a cache set

Answer 10

A group of blocks/lines

Question 11

What is a cache way?

Answer 11

Number of blocks in a set

Question 12

When does a n-way become fully associative

Answer 12

When the number of blocks in a set (n) is the same amount as blocks in the cache. Set = 1

Question 13

When does a n-way become directly mapped?

Answer 13

Number of blocks equals the number of sets

Question 14

What is cache replacement

Answer 14

Replacing one cache block with a new clock from memory

Question 15

Name some replacement polisies?

Answer 15

LRU (Least recently used)
FIFO (First-in-first-out)

Question 16

Describe the LRU replacement policy

Answer 16

Evict the cache vlock that hasn’t been accessed in the longest.

Relies the past behaviour to predict the future

Complex to implement

Question 17

Describe the FIFO replacement policy

Answer 17

Need to remember the order of which the blocks were stored into the cache.

Simpler to implement

Not the best for performance. As a block that was introduced early, might be used very frequently. When the cache is full, this might therefor be evicted although it is used a lot.

Question 18

What are the two ways of writing modified data to memory?

Answer 18

Write-back
Write-through

Question 19

What is write-back?

Answer 19

Write the modified data to memory when the block is evicted from cache.

Question 20

What is write-through?

Answer 20

Write the modified data to memory while writing to cache.

Question 21

What are the advantages and disadvantages with using write-backs

Answer 21

Pro: If the same cache line is written to multiple times - this inly needs to be written to memory once, saving energy and bandwith.

Con: need to track which bytes has been written to, content of memory and cache is not the same. Need a dirty bit for each block

Question 22

What are the advantages and disadvantages with using write-throughs

Answer 22

Pro: simpler implementation and coherence.

Con: slow (write back is as slow as writing to memory, because execution won’t finish until memory-write is done), bandwith intensive

Question 23

How do measure cache performance?

Answer 23

AMAT (avarage memory access time)

AMAT = (hit rate * hit-time) + (miss rate * miss-latency)

Question 24

Why do we use multiple levels of caches instead of one big cache?

Answer 24

Large caches has larger hit-latencies. Hit hit-rate is high, reducing hit-latency increases performance.

Want to balance capacity and access latency.

Also, if a miss happens with multiple caches, the data can be fetched from a lower level cache instead of the memory directly.

Question 25

Why do we need virtual memory?

Answer 25

Capacity and safety

Solves the problem of capacity. A program’s access space can be bigger than the physical memory available. This allows you to run program that are bigger than the amount of physical memory you have. Gives the illusion that a program has access to the full memory.

Prevents programs to overwrite other programs memory, by sharing the physical memory in a safe and efficient way. Prevents program from accessing memory used by OS. Controls access by one program to the memory space of another program.

Question 26

How does virtual memory work?

Answer 26

Implements a virtual address space, that is visible to the programmer.
(PC, load/store addresses)

Physical address space - actual addresses of physical memory.

Address translation - virtual addresses are translated to physical addresses. Done by OS and hardware.

Parts of virtual address space that are not used recently will be stored on disk, as it won’t fit in memory.

Question 27

What are the two types of address translation?

Answer 27

paging: Translation units are fixed size memory regions called pages

Segmentation: Translation units are variable size memory regions, called segments.

Question 28

Describe how paging work

Answer 28

All work is done on fixed sized pages (virtual pages - page frames).

Page tables: Each program has its own page tables, that mappes virtual pages to page frames in memory

Question 29

What do you need to think about when choosing page size

Answer 29

Want them to be large enough to compensate for the expensive first-byte fetch.

Smaller sizes result in more entries in the page table (for translation)

With big pages, might only use small part of their data

Question 30

Who handles page translation when a page is stored in memory

Answer 30

Hardware/OS

Question 31

Who handles page translation when a page is stored on disk?

Answer 31

OS virtual memory manager

Question 32

How are pages translated?

Answer 32

Virtual address: offset + page nr.

Offset: where the byte is within a page.

Offset is 10 bits -> can have 1KB pages

the offset is the same in the virtual address space and the physical one

Page nr.: 22 bits -> 4M pages

The virtual page number needs to be translated to the physical page number

Question 33

What does the page table consist of?

Answer 33

Each entry has status bits and a frame number (physical page number)

Page table is stored in memory. Because of this, the page table itself has an address. Each programs page table has their own address. The address of a processes page tables is stored in a page table base address register. The entry in this register contains the base address of the page table, belonging to the process currently being run.

add the virtual page nr (from the virtual address) to the base address. Table entry at this location tells where physical page is.

If the status bit for this page table entry is 0, this means the page has not been fetched from disk

Question 34

What is a problem with one level page tabels?

Answer 34

One leve l page table reserves space for all possible virtual pages, though all of them may not be used.

Require a lot of memory to store page tables. If a lot of processes are running, all of these need their own page table.

Question 35

What is multi level page tables?

Answer 35

Last level holds address of physical page.

A table entry holds pointer to table entry in next level table.

For example for a two level tables. On the second level, only one of two tables are inserted at the beginning. The other table is not inserted unless the corresponding part of the address space is in use - saves memory space

Virtual address is parted into the number of levels. The first bits are used to find address in first level table, and second bits to find entry in second table.

Multi level page tables saves memory as long as a process does not use its whole virtual space.

Question 36

What are a problem with page tables?

Answer 36

Memory latency.
Page table is in memory, needs one access to fetch physical frame address.Then another access to fetch the data itself

Question 37

How can you solve memory latency caused by page tables?

Answer 37

Using a TLB (Translation lookaside buffer)

Question 38

What is a translation lookaside buffer (TLB)?

Answer 38

Cache for page tables
Holds translations
On TLB miss - access page table and save translation in TLB

Question 39

Describe the full flow of virtual memory

Answer 39

Get virtual page from CPU

Divide virtual address to page number and offset

Go to TLB to see if it has translation. TLB does not have info on pages that has not yet been brought from disk to memory. Only translate pages that are in memory.

If not, go to page table and see if it has translation. A translation is present if the data has been moved from disk to memory (valid bit = 1).

Question 40

How does translation work in 2- level page tables?

Answer 40

Virtual address: 1/2 page number + 1/2 page number + offset

Base address points to first address for 1st level table

first 1/2 page number: add to base address to get entry of pointer to next table

second 1/2 page number: add to pointer from previous table to get entry containing physical page