MICROPROCESSORS Flashcards
(170 cards)
1
Q
Also known as “chip” or “microchip”.
A
INTEGRATED
CIRCUIT
2
Q
IC is a device that integrates both active components and ____ components.
A
passive
passive components (resistors, capacitors, etc.,)
active components (transistors, diodes, etc.,)
3
Q
they require energy to turn ON
A
active components
4
Q
they are always ON
A
passive components
5
Q
Which of the following is NOT an advantage of an Integrated Circuit?
- Lower cost
- Large increase in reliability
- Drastic increase in size and weight
- Possible improvement in circuit performance
A
Drastic increase in size and weight
IC’s are made to be small and compact
6
Q
In Integrated Circuits, a FET functions as an _________
A
Inductor or Coil
Since coils or inductors cannot be fabricated for IC’s as they are size dependent, FETs are used instead
7
Q
FUNCTIONS of an IC
Op amps, Microwave amps, Microwave amps, Voltage comparators, Small signal amplifier, RF and IF amplifier, Multiplexer, Voltage Regulator
A
Linear or Analog IC
8
Q
FUNCTIONS of an IC
logic gates, flip flops, counters, clock chips, calculator
chips, memory chip, microprocessor
A
Digital IC
9
Q
measure of noise immunity
A
NOISE MARGIN (VN)
10
Q
Nominal Volt
- BJT
- Educational use
- COMMONLY: Schottky TTL
A
TRANSISTOR-TRANSISTOR
LOGIC
11
Q
The range of voltages between VL(max) and VH(min) are
A
unacceptable
12
Q
+5V or Vcc
A
NOMINAL VOLT
13
Q
- Industry use
- Easily affected by ESD
- Lower power consumption and higher fan-out
A
(CMOS)
COMPLEMENTARY METAL OXIDE
SEMICONDUCTOR
14
Q
ESD stands for ________
A
Electrostatic Discharge
15
Q
max. # of load ouput gates
A
fan-out
16
Q
max. # of input gates
A
fan-in
17
Q
A
18
Q
Which is true for SPEED-POWER PRODUCT?
* the lower the better
* the higher the better
A
the lower the better
Speed-power product is defined as the product of propagation delay time in ns and power dissipation in mW
19
Q
the product of propagation delay time in ns and power dissipation in mW
A
SPEED-POWER PRODUCT
20
Q
the ratio of time a load or circuit is ON compared to the time the load or circuit is OFF
A
DUTY CYCLE
21
Q
Duty Cycle
In a certain digital waveform, the period is four times the pulse width. The duty cycle is ________.
A
25%
22
Q
A certain gate draws 1.8µA when its output is HIGH and 3.3µA when its output is LOW. What is the average power dissipation if Vcc is 5V and the gate is operated on a 50% duty cycle?
A. 14 µW
B. 1.27 µW
C. 12.75 µW
D. 5 µW
A
C. 12.75 µW
Pave = ((ICCH + ICCL)/2) * Vcc
23
Q
For a CMOS gate, which is the best speed-power product?
A. 1.4 pJ
B. 1.6 pJ
C. 2.4 pJ
D. 3.3 pJ
A
1.4 pJ
“the lower, the better”
24
Q
The active switching element used in all TTL circuits is the ______.
A. bipolar junction transistor (BJT)
B. field-effect transistor (FET)
C. metal-oxide semiconductor field-effect transistor (MOSFET)
D. unijunction transistor (UJ)**
A
bipolar junction transistor (BJT)
25
Which one of the following is **not an example** for low power
Schottky TTL?
a. 740L
b. 74LS193
c. 74LS02
d. None of the above
**740L**
| ***with LS - Low Power Schottky***
26
Which of the following logic families has the **highest maximum clock frequency?**
A. S-TTL
B. AS-TTL
C. HS-TTL
D. HCMOS
AS-TTL
27
Which of the following logic families has the **shortest propagation delay?**
A. S-TTL
B. AS-TTL
C. HS-TTL
D. HCMOS
AS-TTL
28
Which of the following logic families has the **highest noise margin?**
A. TTL
B. LS-TTL
C. CMOS
D. HCMOS
HCMOS
29
Which of the logic families allows the highest operating frequency?
ECL
| Emitter Coupled Logic
30
Why is the fan-out of CMOS gates **frequency dependent?**
A. Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate.
B. When the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will
be one-half of normal; this defines the upper operating frequency.
C. The higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.
D. The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the
number of loads that may be attached to the output of the driving gate.*
The input gates of the **FETs** are predominantly **capacitive**, and as the signal frequency increases the capacitive loading also increases, thereby limiting the
number of loads that may be attached to the output of the driving gate.
31
In CURRENT SOURCING:
Driving gate _______ current to load gate in HIGH state
supplies (source)
32
In CURRENT SINKING:
Driving gate _______ current from load gate in LOW state
receives (sinks)
33
How many output states does a Totem Pole have?
**2** output states (HIGH & LOW)
34
A _________ transistor
controls which transistor is active.
phase splitter
35
Which TTL OUTPUT CONFIGURATION does have this advantages?
* Changes state **faster than open-collector** outputs
* **No external components** are **required**
TOTEM POLE
36
________ standard TTL output configuration with a HIGH output and a LOW output transistor, **only one of which is active at any time.**
TOTEM POLE
37
A circuit that **has** **LOW-state output** circuitry, but **no HIGH-state output** circuitry requires an external pull-up resistor to enable the output to produce a HIGH-state
OPEN COLLECTOR:
## Footnote
OPEN COLLECTOR: only 1 output state (LOW)
38
An OPEN COLLECTOR is used to _________ more current
sink
39
An **open collector** output can _____ current, but it cannot ______
A) sink, source
B) source,sink
C) supply, source
D) sink, receive
sink, source
| An open collector output can sink current, but it cannot source
40
This **TTL Output Configuration** can **can drive their output either HIGH or LOW**, but they **also have a control input** that overrides the effect of the other inputs and places the gate output in a **THIRD STATE or HIGH Impedance State**
TRI-STATE BUFFER
41
R/W stands for
Read/Write
42
EN stands for
Enable
43
The bipolar TTL logic family that was developed to **increase switching speed** by **preventing transistor saturation** is:
A. emitter-coupled logic (ECL)
B. current-mode logic (CML)
C. transistor-transistor logic (TTL)
D. emitter-coupled logic (ECL) and transistor- transistor logic (TTL)
emitter-coupled logic (ECL) and transistor- transistor logic (TTL)
43
An Emitter Coupled Logic has the ______ propagation delay
shortest
44
In a TTL circuit, VOH drops below VOH(min) if an __________ number of load gate inputs are connected.
excessive
45
A classification of IC’s with complexities of **12 to 100** equivalent gates on a chip is known as ___________
A. SSI - Small Scale Integration
B. MSI - Medium Scale Integration
C. LSI - Large Scale Integration
D. VLSI - Very Large Scale Integration
MSI
## Footnote
SSI: <30
MSI: 30 - 100
LSI: 100 - 100,000
VLSI: >100,000
46
Which is not an output state for tristate logic?
A. active HIGH
B. active LOW
C. Low-Impedance
D. High-Impedance
Low-Impedance
| 1 - HIGH, 0 - LOW, Z - High Impedance
47
The application of feedback in **digital electronics** is:
store data
| analog - error correction, digital - data storage
48
**digital circuits** that **use clock signals** to determine the timing of their operations
SYNCHRONOUS
LOGIC CIRCUIT
49
**digital circuit** that **has no memory**, timing
and feedback, and depends on instantaneous state
COMBINATIONAL LOGIC CIRCUIT
Combinational circuits are usually asynchronous.
50
an electronic machine that automatically processes data by the use of digital techniques.
COMPUTER
51
A machine that processes data according to a list of internally stored instruction called programs.
COMPUTER
52
ELEMENTS of a microcomputer
"MMIOH"
Memory
MPU
I/O
HDD - external device
53
A parallel line wire used to carry data or electrical signal.
BUS
54
Bus is Composed of?
*"(ADC)"*
**A**ddress Bus
**D**ata Bus
**C**ontrol Bus
55
Is used to hold data, program or instruction
MEMORY
56
# Memory Performance
BWATSi or BWATC
Memory **B**and**W**idth
Memory **A**ccess **T**ime
Memory **C**apacity
57
Refers to no. of bytes a memory can transfer
Memory Bandwidth
58
Time memory is accessed until DATA is available
Memory Access Time
59
Memory Size
Memory Capacity
60
_____ = (2^n)(bit width)
**SIZE** = (2n)(bit width)
## Footnote
n = no. of bits
2^n = no. address lines
bit width = no. of data lines
61
1 nibble = __ bits
2 nibble = __ bits = __ Byte
1 word = __ bits = __ Bytes
1 nibble = **4** bits
2 nibble = 8 bits = **1** Byte
1 word = **16** bits = **2** Bytes
62
# Types of Memory:
* Directly accessible by MPU
* Used by MPU when performing instructions
MAIN/PRIMARY MEMORY OR ADDRESSABLE
## Footnote
TYPES OF MAIN MEMORY
* Read-Only Memory (ROM)
* Random-Access Memory (RAM)
63
* program memory
* **Non-volatile** (retain data if power is OFF)
* It’s **READ only**; holds program and instruction
ROM
64
# TYPES OF ROM:
It is **Programmed** **upon manufacturing**
(ROM) MASKED ROM
65
# TYPES OF ROM:
**Programmed** by user **but ONCE only**
**(PROM)** PROGRAMMABLE ROM / ONE TIME PROGRAMMING **(OTP)**
66
# TYPES OF ROM:
* Uses **UV RAYS** to erase whole content
* **Needs to be removed** from circuit
(EPROM) ERASABLE PROM
67
# TYPES OF ROM:
* **Uses electrical signals** available in computer to **erase the whole content**
* **No need to remove** from circuit
**(EEPROM)** ELECTRICALLY EPROM
68
# TYPES OF ROM:
**Erases portion** of content
**(EAPROM)** ELECTRICALLY ALTERABLE PROM
69
# Types of Memory:
* **volatile**
* can be **READ or WRITE**; holds program and instruction
RANDOM-ACCESS MEMORY
70
# TYPES OF RAM
**Uses flipflops (F/F)** to store bit value
(SRAM) STATIC RAM
71
# TYPES OF RAM
* **Uses capacitors (and transistors)** to store bit value
* Requires **periodic refreshing**
(DRAM) DYNAMIC RAM
## Footnote
REFRESH MODE:
A. BURST – Refresh All
B. DISTRIBUTED – Refresh specific location
72
# TYPES OF RAM
**FASTER** BUT **EXPENSIVE**
SRAM
73
# TYPES OF RAM
has **HIGHER CAPACITY**; used in computer memory
DRAM
74
# Types of Memory
* **HIGH SPEED**
* Small amount of memory used to **hold frequently accessed data**
CACHE
MEMORY
## Footnote
**IT CAN BE:**
i. DATA
ii.INSTRUCTION
iii. BOTH
75
# CACHE MEMORY
* **Inside MPU**; speed comparable to MPU
* **Faster**
PRIMARY or **LEVEL 1 (L1) CACHE**
76
# ****
* Between MPU and RAM; **speed comparable to SRAM**
* **Bulky** and **slightly slower**
SECONDARY or **LEVEL (L2) CACHE**
77
# Types of Memory
Used by MPU **when computation or process is in progress**
REGISTERS / PROCESSOR MEMORY
78
# Types of Memory
High-speed, large capacity, **non-volatile (flashdrive)**
R / W (READ / WRITE) SEMICON MEMORY
79
EEPROM – Erase at _____ LEVEL
FLASH MEMORY – Erase at _____ LEVEL
EEPROM – Erase at **BYTE** LEVEL
FLASH MEMORY – Erase at **BLOCK** LEVEL
80
* It is **a FIFO device**
* Used to **translate virtual** memory **into physical** memory
MEMORY MANAGEMENT UNIT
(MMU)
81
**Technique** used to transfer data IN/OUT computer system
INPUT/OUTPUT
I/O
82
# DATA TRANSFER Using Physical I/O
MPU executes program for memory and I/O
PROGRAMMED I/O
83
# PROGRAMMED I/O
external device must be always ready to accept data
UNCONDITIONAL
84
The process of **jointly establishing communication** is called:
handshake
85
# PROGRAMMED I/O
uses handshake
CONDITIONAL
86
# DATA TRANSFER Using Physical I/O
I/O space is **separated to memory space**
STANDARD / ISOLATED I/O
87
# DATA TRANSFER Using Physical I/O
I/O Space is **within the memory space** and uses Address Bits (MSB) to access value
. MEMORY-MAPPED I/O (MMIO)
88
# DATA TRANSFER Using Physical I/O
a device **initiates I/O transfer**
INTERRUPT I/O
89
# INTERRUPT I/O
initiated by external device
EXTERNAL INTERRUPT
90
# INTERRUPT I/O
initiated by MPU itself
INTERNAL INTERRUPT
91
A basic computer does not include:
A. an arithmetic logic unit
B. a control unit
C. peripheral units
D. a memory unit
pheripheral units
| external devices
91
**Select the statement that best describes Read-Only Memory (ROM).**
A. nonvolatile, used to store information that changes during system operation
B. nonvolatile, used to store information that does not change during system
operation
C. volatile, used to store information that changes during system operation
D. volatile, used to store information that does not change during system operation*
ROM - **nonvolatile**, used to store information that **does not change** during system operation
92
**Dynamic** memory cells store a data bit in a ______.
capacitor
93
**Static** memory cells store a data bit in a ______.
flip-flop
94
A **major disadvantage** of the **mask ROM** is that it:
A. is time consuming to change the stored data when system requirements change
B. is very expensive to change the stored data when system requirements change
C. cannot be reprogrammed if stored data needs to be changed
D. has an extremely short life expectancy and requires frequent replacement
**cannot be reprogrammed** if stored data needs to be changed
95
Which of the following computer memories is fastest?
A. Cache
B. Primary
C. Mass storage
D. Off line back up
Cache
## Footnote
A. Cache - 1st
B. Primary - 2nd
C. Mass storage - 3rd
D. Off line back up - 4th
96
Most devices are interfaced to a bus with _______. It’s also a type of circuit used at the interface point of an input port.
A. totem-pole outputs
B. tri-state buffers
C. pnp transistor
D. resistors
tri-state buffers
## Footnote
input port - tri-state buffers
output port - latch
97
An **I/O processor** control the flow of information between:
A. cache memory and I/O devices
B. main memory and I/O devices
C. 1 Two I/O devices
D. cache and main memories
main memory and I/O devices
98
Polling is the method used for:
A. determining the state of a microprocessor
B. establishing communication between CPU and a peripheral
C. establishing a priority for communication with several peripherals
D. determining the next instrcution
establishing a **priority** for communication with several peripherals
## Footnote
Polling
- periodically checks the device status
- best used when no priorities
99
The **technique of assigning** a memory address to **each I/O device** in the computer
system is called:
A. memory-mapped I/O
B. ported I/O
C. dedicated I/O
D. wired I/O
memory-mapped I/O
100
a device that can be programmed with series of
instructions to perform specified functions of data.
MICROPROCESSOR (MPU)
101
# ELEMENTS OF MPU
ABCR
* **A**rithmetic & Logic Unit (ALU)
* **B**us Interface Unit (BIU)
* **C**ontrol Unit (CU)
* **R**egisters
## Footnote
**ALU (Arithmetic & Logic Unit)**- define size of MPU; computational engine
**CU (Control Unit)-** direct sequence of operation; select which elements are needed
**BIU (Bus Interface Unit)-** performs memory addressing
102
(CISC) **Complex** Instruction Set Computer
* **Single Bus** Architecture
* Used by MPU (**Multitasking**)
* FETCH-EXECUTE
VON NEUMANN
ARCHITECTURE
103
(RISC) **Reduced Instruction** Set Computer
* **Dual Bus** Architecture
* Used by **MCU** (**1 task at a time**)
HARVARD
ARCHITECTURE
104
SoC means
System on a Chip (SoC)
105
* complete package in a single chip
* employed on embedded system
* ROM CAPACITY > RAM CAPACITY (in kB)
MICROCONTROLLER (MCU)
106
Which of the following are the three basic sections of a microprocessor unit?
A. operand, register, and arithmetic/logic unit (ALU)
B. control and timing, register, and arithmetic/ logic unit (ALU)
C. control and timing, register, and memory
D. arithmetic/logic unit (ALU), memory, and input/output
control and timing, register, and arithmetic/logic unit (ALU)
107
What is occurring **when two or more sources of data attempt to use the same bus**?
A. Bus contention
B. Direct memory access
C. Bus interruption
D. PPI
Bus contention
108
The _____ **ensures that only one IC is active at a time** to avoid a bus conflict caused by two ICs writing different data to the same bus.
A. control bus
B. control instructions
C. address decoder
D. CPU
address decoder
109
Microprocessors and memory IC’s are generally designed to drive only a single TTL load. Therefore, **if several inputs are being driven from the same bus, any memory IC must be:**
A. buffered
B. decoded
C. addressed
D. stored
buffered
110
Under Interrupt I/O, an **external device can force the microcomputer system to stop executing** the current **program temporarily** so that it can execute another program known as the:
A. internal interrupt
B. interrupt service routine
C. sub-routine instruction
D. call delay instruction
interrupt service routine
111
A register in the microprocessor that keeps track of the answer or results of any arithmetic or logic operation is the:
A. stack register
B. program counter
C. instruction pointer
D. accumulator
accumulator
112
Indicates the status of an operation through flags
STATUS REGISTER
113
an indicator that uses 1 or 0
FLAGS
114
6 BASIC FLAGS (cannot be changed by the user):
| CONDITIONAL FLAGS
* Z (Zero Flag)
* O (Overflow Flag)
* S (Sign Flag)
* P (Parity Flag)
* C (Carry Flag)
* H (Hot-Carry)
115
Flags that can be changed by the user (DTI)
| CONTROL FLAGS
* **Direction Flag** – for strings
* **Trap Flag** – for interpreter (execute instruction line by line)
* **Interrupt Flag**
116
FIFO is formed by an arrangement of :
A. diodes
B. transistors
C. MOS cells
D. shift registers
shift registers
117
A programming language that uses *English-like* words and has a **one-to-one correspondence** to machine language refers to
A. assembly language
B. Firmware
C. high-level language
D. interpreter
assembly language
118
A **microprocessor** is generally:
A. single chip SSI
B. single chip MSI
C. single chip LSI
D. any of the above
single chip LSI
| MPU - LSI
119
The remaining address line of _____ bus is decoded to generate chip select signal.
A. Data
B. Address
C. Control bus
D. Both (a) and (b)
address
120
Used to store critical pieces of data during subroutines and interrupts:
Stack
121
Zero address instruction format is used for
Von-Neuman architecture
RISC architecture
CISC architecture
Stack-organized architecture
Stack-organized architecture
122
________ is usually the first level of memory access by the microprocessor
Cache Memory
123
Microprocessor reference that are available in the cache are called______
Cache hits
| not available -cache misses
124
Which are the two main components of the CPU?
Control unit and ALU
125
Registers, which are partially visible to users and used to hold conditional, are known as
General purpose register
126
The metal disks, which are permanently housed in, sealed and contamination free containers are called
Winchester disk
127
The instructions for starting the computer are house on
Read only memory chip
128
The ALU of a computer normally contains a number of high speed storage element called
Registers
129
To locate a data item for storage is
Fetch
130
Which of the following terms is the most closely related to main memory?
a. Non volatile
b. Permanent
c. Control unit
d. Temporary
d. Temporary
131
The register section is related to________of the computer
Main memory
132
In Microprocessor one of the operands holds a special register called
Accumulator
133
a subsystem that transfer data between computer components inside a computer or between computer:
Bus
134
Which memory is used to hold the address of the data stored in the cache
Associative memory
135
A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following modes this SRAM is operating
Write
136
The first modern computer was called
ENIAC
137
The time required to refresh a typical DRAM is
2-4 ms
138
The no. of address lines required to address a memory of size 32 K is
15
139
A floppy disk is used in a microprocessor based system as
I/O Device
140
A system of letters ,symbols used by the microprocessor manufacturers as an abbreviated form of an instruction is called
mnemonic
141
Which microprocessor architecture is used in most personal computers and servers today?
CISC(Complex Instruction Set Computing)
| Von Neumann
142
The microprocessor's clock speed is measured in:
Gigahertz (GHz)
143
Which microprocessor architecture is commonly used in mobile devices and embedded systems?
ARM (Advanced RISC Machine)
144
The concept of "big-endian" and "little-endian" relates to:
Data storage order in memory
145
In a microprocessor, the "stack" is typically used for:
Temporary data storage and managing subroutine calls
146
Which microprocessor mode allows privileged operations and direct access to hardware?
Kernel Mode
147
Which microprocessor feature allows multiple instructions to be executed simultaneously, improving performance?
Pipelining
148
What is the Von Neumann Architecture?
SISD(Single Instruction, Single Data)
149
Most common access technique in CPUs
LIFO
150
Two most common stack operators
Push and Pop
151
Stack-organized computeruses instruction of _______
Zero Addressing
152
Speed of Supercomputer is measured in
FLOPS
| Floating Points Operations Per Second
153
An early form of Random Access Memory (RAM)
Magnetic Core Memory
154
It is a small-sized type of volatile computer memory that provides high-speed data access to the CPU
Cache Memory
155
It is a type of non-volatile memory that uses a thin film of a magnetic material to hold small magnetized areas, known as bubbles, which each store a bit of data.
magnetic Bubble Memory
156
Widely used as main computer's main memory
DRAM
157
Permanent memory of a computer
ROM
158
The electronic circuitry that executes instructions in a computer programme is known as
central processing unit (CPU)
159
Operations mainly performed by RAM
Read and Write
160
The organization and inter connection of the various components of computer system is
Architecture
161
is a special type of memory that works like both RAM and ROM
Flash Memory
162
Smallest and fastest memory in computer
Register memory
| faster than cache
163
Arrange the following computer memory types from fastest to slowest
speed:
(A) Hard Disk
(B) Main Memory (RAM)
(C) CD-ROM
(D) CPU Registers
(E) Cache Memory
D, E, B, A, C
164
POST
Power-On Self-Test
165
The first instructor of bootstrap loader program of an operating system is stored in
BIOS(Basic Input/Output System)
166
A small program that is responsible for loading the operating system into memory
Bootstrap Loader
167
A tiny bootsrap loader program is situated in
ROM
168
Bits used when cache location is updated
Dirty bit
