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Mod 4 #2 > Mod 4 #2 > Flashcards

Mod 4 #2 Flashcards

(83 cards)

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1
Q

the overall computer system performance, enhanced by a single Improvement is limited by the amount the improved feature is used

A

Amdahl’s law

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2
Q

One operation performed on many pieces of data

A

Short Vector processing

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3
Q

The classification of computer architectures based on instructions and data

A

Flynn’s taxonomy

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4
Q

Two or more processors on a single chip allowing multiple instructions to execute simultaneously

A

Multi-core processing

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5
Q

Increases utilization of a single processor by transferring instructions from multiple threads

A

Multi-threaded processing

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6
Q

Computer systems using multiple processors

A

Multiprocessor systems

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7
Q

Special-purpose processor for graphics also good for Math and encryption

A

Graphics Processing Unit GPU

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8
Q

Integrated circuit configured by the customer using software known as Hardware description language

A

Field programmable gate arrays

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9
Q

What are five segments of memory where programs are loaded

A 
Stack 
freespace 
Heap 
bss 
data
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10
Q

What are two ways to implement the control unit

A

Hardwired and microprogrammed

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11
Q

What CU implementation method does the x86 use

A

Microprogrammed implement the ISA

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12
Q

Which computer architecture uses fixed-length instructions

A

Risc

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13
Q

Which computer architecture uses variable-length instructions

A

Cisc

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14
Q

Which Benchmark for measuring computer systems is favored by computer manufacturers

A

Standard performance evaluation Corporation spec

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15
Q

Which multiprocessor system communicates through memory

A

Symmetric shared memory

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16
Q

Which multiprocessor system communicates through an interconnection

A

Asymmetric multi-processing or distributed shared memory

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17
Q

What bus line is used for interrupts in synchronization

A

Control line

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18
Q

What is the difference between a multi point and point to point bus

A

Multi-point connect more than two components connects only two components

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19
Q

What component is used to connect unlike buses

A

Bridge

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20
Q

What protocol uses asynchronous Communications

A

Serial communication

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21
Q

Which is maskable interrupts or exceptions

A

Both

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22
Q

What is the difference between an interrupt in an exception

A

Interrupt indicates Hardware needs serviced

exception is the byproduct of an error while executing an instruction

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23
Q

What term is used to describe an interrupt or an exception that must be dealt with immediately

A

Non maskable

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24
Q

What vectors of the x86 IDT are non maskable interrupts and exceptions

A

0 through 31

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25
How does the control unit keep the status of a processor when servicing an interrupt
It saves variables and registers to memory
26
What buses are attached to the North Bridge
Memory and digital video
27
What buses are attached to the South Bridge
``` PCI USB SCSI IDE SATA audio ```
28
Which I/O interface category provides serial Communications
Serial
29
Name two I/O interfaces used for video
Video graphics array VGA digital video interface DVI
30
What are the memory hierarchy levels from fastest to slowest access time
``` Registers bit cache byte primary RAM secondary magnet disc external. ```
31
Which of the three cache a methods of replacement requires a history or frequency of used blocks
Least recently used lru
32
Which of the two cache mapping schemas require searching to find the correct block
Associative
33
Updates the Block in main memory when the cash block becomes a victim block
Wright back
34
Independent cache for data and instructions one or the other but not both
Harvard cache
35
A virtual address is known as what
A page
36
A physical address is known as what
A frame
37
Random access memory RAM allows for reading and writing data what are the two types
Static Ram sram Dynamic Ram dram
38
Made of D flip flop circuits that hold data as long as there is power e.g. cache memory
Static Ram
39
Made of little batteries that leaked electricity called capacitors the most common main memory solution is double data rate a type of synchronous dram that returns double the data
Dynamic Ram
40
Read-only memory ROM is non-volatile and consist of what
Programmable ROM erasable programmable ROM EPROM ELECTRICALLY ERASABLE PROGRAMMABLE ROM EEPROM
41
The sector portion of a platter traditionally holds how many bytes of data
512
42
Disk performance is measured by what
``` Spin up time seek time rotational latency transfer time disk access time ```
43
What RAID level is generally used for file servers
Raid 5
44
Connects the internal components of a computer and moves data back and forth
Bus
45
Form and method that computer components use to transmit data between the sender and receiver
Bus protocol
46
Allows for communication between dissimilar buses
Bridge
47
Physical means for the peripheral devices to interface with the computer also referred to as ports
Device interface
48
Processor memory and bus on the same ship
SOC system on a chip
49
series of steps to coordinate a synchronous Communication in which the sender and receiver proceed to The Next Step only when both parties agree that the current step was completed
Hand shaking
50
The act of temporarily storing data in a region of physical memory called a buffer
Buffering
51
system for resolving bus control conflicts and assigning priorities to bus control request in a multi-point bus topology where there is more than one Master
Bus arbitration
52
A synchronous event typically triggered by an IO device
Interrupt
53
Synchronous event resulting from the execution of an instruction that disrupts program execution
Exception
54
time it takes memory to Output set data once the memory controller receives a data request its measured in bus clock Cycles before main memory returns data
Latency
55
Rate at which data is loaded from in stored to memory memory bandwidth measures and bits per second
Throughput
56
What type of memory is memory that can be lost
Volatile memory
57
When the needed data is in the cache
Cache hit
58
When a block in cache is selected for replacement
Victim block
59
Instead of transferring only the data needed this transfers the entire block of data
Locality principle
60
A concentric circle on the platter
Track
61
A combination of tracks across all platters
Cylinder
62
Made of flash memory in common replacement for disks built on arrays of nand or nor memory circuits
Solid state drive SSD
63
Can an IO module have more than one device in their face
Yes
64
Is the CPU connected to the same bus as memory
No
65
What component is needed to connect the memory bus and the io bus
Bridge
66
Which of the two communication categories uses sequential groups of bits via multiple data lines and also uses synchronous communication
Parallel Communications
67
which of the three types of bus arbitrations connect devices in a series with Device closest to the Arbiter getting control of the bus
Daisy chain
68
Which of the three types of bus arbitration uses priorities which are assigned to each device on the bus
Distributed using self-selection
69
Which of the four IO control methods requires more overhead of the processor
Programmed IO
70
What are the three classes of exceptions
Faults traps aborts
71
What is an example of a non maskable exception
Division error
72
Which of the four IO control methods requires each IO device to have an allocated segment of memory
Memory mapped
73
What is the last step performed by the device to terminate dma
Acknowledge notify the processor of completion
74
What is an example of a bus that uses asynchronous Communications
SATA
75
Where is the cache physically located within the computer
CPU
76
What two attributes does the tlb map
Page and frame
77
From which of the three types of ROM is flash memory created
EEPROM
78
General purpose register used for any purpose stores data or address is for the programmer
GPR general purpose register
79
These are special purpose registers for One Singular purpose
Segment register
80
Holds info about the most recently performed ALU operation memory alignment endianness and disabling of interrupt and sets processor operating mode
Status and control registers
81
Dictates which instructions in architectural features are available
Moods of operation
82
Ensure security of the system through process isolation
Privilege levels
83
Most frequently used instructions data is moved from register to register in register to memory
Data movement instruction

Mod 4 #2 (1 decks)

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