Processors and the Fetch-Decode-Execute Cycle

Question 1

Accumulator

Answer 1

Stores the result of the ALU’s most recent operation

Question 2

Arithmetic Logic Unit

Answer 2

Performs all of the CPU’s arithmetic and logical functions

Question 3

Cache Memory

Answer 3

Low-capacity, high-speed memory that stores frequently used instructions and data

Question 4

CISC

Answer 4

Instruction set where different instructions may require a different number of fetch–decode–execute cycles to run

Question 5

Clock Speed

Answer 5

Frequency at which the CPU can carry out operations

Question 6

Core

Answer 6

Processor within a CPU which can run a single instruction at a time

Question 7

Current Instruction Register

Answer 7

Holds the instruction that the CPU is currently executing

Question 8

Fetch-Decode-Execute Cycle

Answer 8

Sequence that is constantly repeated by the computer in order to carry out instructions

Question 9

Harvard Architecture

Answer 9

Computer architecture where data and instructions are stored in separate locations

Question 10

Instruction Set

Answer 10

List of all machine code commands that are recognised by a particular CPU

Question 11

Memory Address Register

Answer 11

Holds the memory address that needs to be accessed

Question 12

Memory Data Register

Answer 12

Holds the data that has just been loaded from, or is about to be saved to, memory

Question 13

Multicore System

Answer 13

Computer that uses multiple processors

Question 14

Opcode

Answer 14

Part of machine instructions that specifies the operation to be performed

Question 15

Operand

Answer 15

Part of machine instructions that specifies the value to be used

Question 16

Parallel System

Answer 16

Computer system that can carry out multiple operations simultaneously

Question 17

Pipelining

Answer 17

Technique for implementing instruction-level parallelism within a single processor in order to improve performance

Question 18

Program Counter

Answer 18

Register that is incremented in each iteration of the fetch–decode–execute cycle

Question 19

Register

Answer 19

Low-capacity storage locations within the CPU that are used in the fetch–decode–execute cycle

Question 20

RISC

Answer 20

Instruction set where different instructions require the same number of fetch–decode–execute cycles to run

Question 21

Von Neumann Architecture

Answer 21

Computer architecture based on the stored-program computer concept; data and instructions are stored together