SPLDs, CPLDs, FPGAs Flashcards
(27 cards)
What does SPLD stand for?
Simple programmable logic devices
What is an SPLD?
This is a chip that has an undefined function when manufactured and are used to implament digital circuits
What are some basic parameters of SPLDs?
> Number of gates
Number of IO
Max operating frequency
What are the two types of SPLDs?
> Programmable array logic (PAL)
> General array logic (GAL)
What is programmable array logic?
> This is an array of fuses, that during programming are broken. The unbroken links allow a SOP expression to be formed
The SOP expression has a limited number of allowed variables
They are only programmable once
What is general array logic?
> Fuses are replaced with transistors that are enabled and disabled at startup using an EPROM or S-RAM
They are reprogrammable
What is a macrocell?
> The outputs of multiple PAL or GALs are connected to a macrocell
The multiple PALs or GALs are connected together with multiple input OR gates
The macrocell also provides additional output logic
Macrocells are also programmable
[Picture1]
What does CPLD stand for?
Complex programmable logic devices
What is a CPLD?
> Made from multiple SPLDs connected with a programmable interconnect
This allows them to perform more logic operations that a single SPLD and fit larger digital circuits onto the CPLD
What is the arrangement of parts of a CPLD?
> There are multiple LABs (Logic array blocks) connected together using a a PIA (Programmable interconnect arrays)
Each lab is formed of a macrocell and SPLDs
[Picture2]
What parts of a CPLD can be programmed?
> The LABs
> The Interconnects
How are CPLDs fromgrammed?
> Reprogrammabled
> Using EEPROMS
What are the aspects of a CPLD Macrocell?
> 5x 5-input AND gate SPLD (GAL)
A product term selection matrix
Expander
What is a product term selection matrix?
This allows different AND gates to be disconnected from the OR gate. For example, if only 3 out of 5 AND gates are used, then they can be disconnected
What does having 5 AND gates limit?
It can produce up to 5 product terms for the output. If more are needed then an expander can be used
What is a shared expander?
This can feed one (AND gate) output back into the input array
What is the benefit of the shared expander?
It avoids replication of terms across the cells and allows SOP expressions with more than 5 inputs to be created
What is a parallel expander?
This is where you arrange CPLDs in parallel allowing macrocell 2s output to include the output from macrocell 1
What does FPGA stand for?
Field programmable gate array
What is an FPGA?
It is similar to a CPLD but has a different architecture.
What is the benefit of an FPGA over a CPLD?
An FPGA has many more equivalent gates that can be made from a CPLD
What are additional elements that can be included in an FPGA?
> Memory blocks > Transceivers > Protcol controllers > CPUs > Additional IP
What does IP stand for, in terms of FPGA additional circuitry?
Intellectual property
What is the benefit of using IP blocks that are unconfigurable?
It removes the need to build everything from scratch
