structure and function of the processor Flashcards
Explain how pipelining in a CPU could speed up the execution of this program.
– An instruction can be fetched as the
previous one is being decoded …
– … and the one before that is being
executed.
Explain the need for the following registers.
(i) Program Counter (PC)
[2]
(ii) Memory Address Register (MAR)
[2]
(iii) Memory Data Register (MDR)
(i)–Is needed to store the address of the next
instruction (to be processed)
–Value is then sent to the MAR
–After sending the value the PC is
incremented / changed to address held in
CIR if the operation is a Jump
(ii)– Contains the address of the instruction
(to be accessed in memory)…
– …address of instruction sent from PC
– Contains the address of the data (to be
accessed in memory)…
– …address of data sent from CIR
(iii)– Contains the instruction which has been
accessed from memory
– Contains the data which has been
accessed from memory
– That is referenced by the MAR /
Instruction sent to CIR
– acts as a buffer
One feature of Von Neumann architecture is that instructions are executed in a linear sequence.
(i) Give three other features.
Single control unit
One instruction at a time
Uses fetch execute cycle
Program & data stored together /
program & data in same format
One register holds the address of the next instruction to be processed.
Explain two reasons why the value held may change.
Program Counter increments…
…during f-e cycle
A jump instruction from the Current
Instruction Register / operand…
… program Counter changes to
address given
Describe two ways in which the accumulator is used.
Temporary storage
for data being processed / during
calculations
I/O in processor…
… used as a buffer / gateway
