synchronous circuits Flashcards
(14 cards)
what is a gate delay?
when an input to a logic gate changes, the get takes some time to respond and make its output valid.
this time is the gate delay
what is the validity of the signal before the gate delay?
if the input to a logic gate changes, you cannot rely on the output until the gate delay has elapsed
if the signal is invalid, does it mean it is wrong?
it means that it is not guaranteed to be correct
what is a glitch?
for a short time, the output of the circuit is incorrect, but if you wait a short time, it will reach the correct value.
what is a dff (delay flip flop)
a dff is a circuit that remembers one bit of data (the “state”)
there is a data input x carrying a value to be remembered, and a data output y conveying the state value
as well as a clock tick
what is special about the clock tick?
there is one global click signal, which is sent to all flip flops of the circuit. every flip flop updates its state at the same time
flip flop versus registers
a flip flop remembers a bit for a very short time, just one clock cycle
a register remembers a bit until you tell it to load a new value - controllable memory element
describe the behaviour of a 1-bit register
remebers a bit
receives a control input ld and a data input x, and outputs a 1-bit state
initial value is zero
at each clock tick, the register loads the data value x if ld ==1
if ld==0 the register ignores the value of x and retains previous state
what does the dff do: 1 bit reg?
hold state and load a new state at every clock tick (if ld == 1 new if 0 old state)
how is the dff input finalised?
mux 1
what is the intial state of a simulation table?
”?” - the circuit should never use this value
cycle 0 : ld = 1 x= 1
cycle 1: ld = 1 x = 0
2: 0 1
3 1 1
complete this simulation table
what is the simultaneous update of state?
The state of a circuit consists of the states of all the flip flops
In a digital circuit, all the flip flops change their state simultaneously at the clock tick compared languages like python change one variable and leave all the others unchanged