U15 Hardware and Virtual Machines Flashcards
1
Q
CISC
A
- complex instruction set computer
- designed to carry out a given task with as few lines of assembly code as possible
- CISC processor is based on a complex instruction which needs to be converted by the processor into a number of sub-instructions to carry out the required operation
2
Q
fixed length instructions
A
the amount of memory it will consume is fixed (e.g: 16 bits)
3
Q
variable length instructions
A
can take as much space as it wants
4
Q
hardwired control unit
A
- uses logic circuits
- flip flop
5
Q
programmable control unit
A
uses programs, code will compile, run and generate output
6
Q
features of CISC
A
- larger number of instructions + more complex
- fewer registers => most processing is done in memory
- many instruction formats
- requires more complex circuit
- has more addressing modes
- makes less use of RAM
- poor pipelineability
- uses multicycle and variable length instruction
- has programmable control unit
7
Q
RISC
A
- reduced instruction set computer
- less instruction => better performance from the processor (does not need to break complex instructions)
- assembly code is broken into a number of single cycle instructions
8
Q
features of RISC
A
- fewer instructions
- better pipelineablity
- many registers
- simpler instructions
- few instruction formats
- usually uses single cycle instructions
- uses fixed length instructions
- less complex circuit
- fewer addressing modes
- makes more use of RAM
- has hardwired control unit
9
Q
pipelining
A
- instruction level parallelism => multiple operations are performed in a single cycle
- execution of an instruction is split into number of stages
- when first stage for an instruction is completed the first stage of the next instruction can start executing
- another instruction can start executing before the previous one is finished
- processing of a number of instructions can be done simultaneously
10
Q
alternate method to pipelining
A
- content of five stages can be stored in register
- then the processor can be restored to its previous state once the interrupt has been serviced
11
Q
flynn’s classification
A
- computer architecture
- based on number of instructions and data
- instruction stream: sequence of instructions executed by the processing unit
- data stream: sequence of data or temporary result called by instruction stream
12
Q
single instruction single data (SISD)
A
- only one processor
- processor executes one set of instructions on one set of data
13
Q
single instruction multiple data (SIMD)
A
- uses many processors
- each processor has several ALUs
- each ALU executes the same set of instruction on a different set of data at the same time
14
Q
multiple instruction single data (MISD)
A
- several processors
- each processor executes a different set of instructions on one set of data at the same time
15
Q
multiple instruction multiple data (MIMD)
A
- several processors
- each processor executes a different set of instructions
- each processor operates on a different set of data
