This class was created by Brainscape user Eesha Patel. Visit their profile to learn more about the creator.
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Eesha Patel
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Decks in this class (15)
slides01
Cpu dealing with i o and memory 1,
Steps in interrupt processing 6 2,
Dma direct memory access 3
11
cards
slides02
3 ways of allowing users to inter...,
System calls 2,
Os architectures 3 3
8
cards
slides03
Process 1,
Uniprogramming vs multiprogramming 2,
Process structure in memory 2
13
cards
slides04
Cooperating processes and reasons...,
Two models of ipc 2,
Shared memory 3
10
cards
slides05
Three streams in a process 1,
File descriptor table 2,
Output redirection printing to a ...
8
cards
slides06
Lightweight multi processing 1,
Motivation for lightweight multi ...,
Processes vs threads 3
15
cards
slides07 - Synchronization Techniques
Concurrent processes 1,
Race conditions how to avoid them 2,
Critical section 3
7
cards
slides08 - Synchronization Techniques (2)
Memory barriers 1,
Memory models 2 2,
Test andset tas 3
8
cards
slides09 - Synchronization Problems & Patterns
Blank 1
1
cards
slides10 - File Systems
Directory 1,
Single level directory 2,
Two level directory 3
5
cards
slides11 - File System Implementation
Directory 1,
Two directory implementations 2,
File space allocation methods 3 3
9
cards
slides 12 - Scheduling
Cpu scheduler 1,
Cpu dispatcher 2,
Preemptive vs non preemptive 3
18
cards
slides13 - More scheduling
Multi level feedback queue schedu...,
Real time processes 2,
Rate monotonic scheduling 3
5
cards
slides14 - Memory Management
Memory units that can be directly...,
Address binding 3 2,
Logical vs physical address spaces 3
8
cards
slides 15 - Memory Management (2)
Blank 1
1
cards
More about
COMP310
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