1.1 The characteristics of contemporary processors, input, output and storage devices Flashcards
ALU
Arithmetic & Logic Unit
responsible for performing arithmetic calculations, as well as logical operations Includes: Logical bitwise operations such as XOR AND OR and NOT , comparison between values , shifting binary patterns to the left or right.
Control Unit (CU)
Processor component that is in charge of organizing the sequence in which programs instructions are executed, It directs the operations of the CPU It decodes instructions and fetches any required data.
-It coordinated and controls the activities of the CPU
-manages the controls of data between the CPU and other devices
-accepting the next instruction
-decoding instructions
-storing the resulting data back in memory.
Registers
Small, high-speed storage locations that temporarily hold data and instructions (all arithmetic, logic and shift operations occur in these registers)
Program counter(PC) - Hold the address of the next instruction to be executed.
Accumulator(ACC) - stores the results from calculations done inside the ALU
Memory address register(MAR) - Holds the address of a memory location that has to be read from or written to.
Memory data register(MDR) - Temporarily stores the data that has been read or data that needs to be written to main memory.
Current instruction register- Holds the current instruction that the processor is executing.
Buses
a set of parallel wires which connect two or more components inside the CPU. There are three types
- data bus
- address bus
- control bus
these buses collectively are called the system bus.
The width of the bus is the number of parallel wires the bus has. The width of the bus is directly proportional to the number of bits that can be transferred simultaneously at any given time. buses are typically 8, 16, 32 or 64 wires wide
Data bus
This is a bi-directional bus (meaning bits can be carried in both directions). This is used for transporting data and instructions between components.
Address Bus
This is the bus used to transmit the memory address specifically where data is to be sent to or retrieved from. The width of the address bus is proportional to the number of addressable memory locations.
Control Bus
This is a bi-directional bus used to transmit control signals between internal and external components. The control bus coordinates the use of the address and data buses and provides status information between system components.
Assembly Language
Programming language that has the same structure and set of commands as machine languages but allows programmers to use symbolic representations of numeric machine code and uses mnemonics (ADD for addition)
The instruction is divided into operand and opcode in the Current Instruction Register. The operand contains the data or the address of the data upon which the operation is to be performed. The opcode specifies the type of instruction to be executed.
Pipelining
Is the process of carrying multiple instructions concurrently
each instruction will be on a different stage of the fetch-decode-execute cycle. One instruction can be fetched while the previous one is being decoded and the one before is being executed.
In the case of a branch the pipeline is flushed
-pipelining reduces latency (the amount of time it takes for an instruction to go through the fetch-decide-execute cycle)
-The CPU is not idle while waiting for the next instruction which increases the speed of execution
-The next instruction is fetched while the current one is decoded/executed
-All parts of the processor can be used at any instance in time
Fetch-Decode-Execute Cycle
the sequence of operations that are completed in order to execute an instruction.
Fetch
- Address from the pc is copied to the MAR
- Instructions held at that address (MAR) is copied to the MDR
by the data bus.
- Simultaneously the contents of the pc is incremented by one
- The value held in MDR is copied to CIR
Decode
- The contents in the CIR is split into operands and opcodes
- interpreting the instruction and then reading and retrieving the required data from their addresses
Execute
- The decoded instruction is executed the CPU carries out the required action
Factors affecting CPU performance
Clock speed
-Is determined by the system clock, this is an electronic device which generates signals switching between 0 and 1. All processor activities begins on a clock pulse, and each CPU starts as the clock changes to 0 to 1. The clock speed is the time taken for one clock cycle to complete.
Number of cores
- A core is an independent processor that can perform its own fetch-decode-execute cycle. A computer with multiple cores can complete more then one fetch-execute cycle at any time. A computer with dual cores can theoretically complete tasks twice as fast as a computer with a single core. However, not all programs are able to utilise multiple cores efficiently as they have not been designed to do so, so this is not always possible.
Amount and type of cache memory
-Cache memory is the CPU’s onboard memory. Instructions fetched from main memory are copied to the cache, so if required again, can be accessed quicker, as cache fills up unused instructions are replaced.
Level 1 Cache
Very fast memory cells with a small capacity. (2-64KB)
Level 2 Cache
Relatively fast memory cell, with a medium sized capacity. (256KB-2MB)
Level 3 Cache
Much larger and slower memory cell.
Von Neumann Architecture
Traditional computer architecture that forms the basis of most digital computer systems. A single control unit manages program control flow following a linear sequence of fetch-decode-execute. a shared memory and shared data bus is used for both data and instructions
benefits:
.-Cheaper to develop as the control unit is easier to design
-Programs can be optimised in size
Harvard Architecture
Harvard architecture has physically separate memories for instructions and data, more commonly used with embedded processors.This is useful for when memories have different characteristics, i.e. instructions may be read only, while data may be read-write. This also allows you to optimise the size of individual memory cells and their buses depending on your needs, i.e. the instruction memory can be designed to be larger so a larger word size can be used for instructions.
benefits:
- Quicker execution as data and instructions can be fetched in parallel.
-Memories can be different sizes, which can make more efficient use of space
Contemporary Processor Architecture
Modern high-performance CPU chips used both von Neumann and Harvard architectures in one design. There is one main memory for data and instructions (von Neumann), but cache memory is divided into instruction cache and data cache (Harvard).
