1.1.1 structure and function of processor Flashcards
contains 1.1.1 and assembly code + addressing modes from 1.2 (SLR07)
1
Q
Why was assembly language developed?
A
- allow humans to input instructions easily, without having to remember long strings of 1’s and 0’s.
- allows programmer to write machine code using a set of mnemonics that represent binary equivalent in machine code
2
Q
What are Mnemonics?
A
- Simplified instructions, used in assembly language, to easily write instructions.
3
Q
Give examples of some mnemonics
A
- ADD, SUB, STA (store), LDA(load), BRA (branch always), BRZ(branch if zero), BRP(branch if positive), INP, OUT, HLT (end), DAT(data location), AVG.
4
Q
what does HLT do?
A
- Ends the program
5
Q
what does ADD do?
A
- Adds contents stored in specified memory location (uses operand) to value held in accumulator
6
Q
what does SUB do?
A
- Subtracts contents stored in specified memory location using operand from value held in accumulator
7
Q
what does BRA do?
A
- Always branches to address specified by operand. Unconditional branch
8
Q
what does BRZ do?
A
Branches to address specified by operand if value in accumulator = zero. Conditional branch
9
Q
what does BRP do?
A
- branches to address specified by operand if value in accumulator is 0 or positive. A conditional branch
10
Q
what does STA do?
A
- Copies value held in accumulator to be stored in memory location specified by operand
11
Q
what does LDA do?
A
Loads/copies value from specified memory location given by operand into accumulator
12
Q
what does INP do?
A
Takes an input value from input area and stores into accumulator (opcode is 9 and operand is 01)
13
Q
what does OUT do?
A
- Displays value held in accumulator in output area (opcode is 9 and operand is 02)
14
Q
what does DAT do?
A
- indicate a location that contains data and an optional value for instruction (initialisation: it creates a variable identifier that can be used instead of an address in instructions).
15
Q
where do you put data definitions for LMC
A
- Data definitions go at bottom of program
16
Q
What will this do?
num1 DAT 100
A
- it will map a memory location to identifier num1 and set its initial value as 100.
17
Q
in machine code, there are different types of addressing modes specified by what?
A
- opcode
18
Q
the addressing mode specifies the way in which _________ will be interpreted.
A
- operand
19
Q
what does direct addressing mode do
A
- value in operand is referencing address in memory where the required value is located
20
Q
what does immediate addressing mode do
A
- data to be used is the actual value of the operand.
- often denoted with # in assembly language.
21
Q
what does indirect addressing mode do
A
- value in operand is a reference to memory location that contains address in memory where required value is located
22
Q
why is indirect addressing so useful
A
- large address ranges can be used to reference data and instructions
23
Q
what does indexed addressing mode do
A
- index register = dedicated registers in the CPU.
- Indexed referencing makes use of this register to access array with data in contiguous memory locations.
24
Q
if operand is 1010 and index register stored value 0011, what would happen using indexed addressing if instruction is ADD 10
A
- operand specifies that memory location to be used is 10. it finds value in location and adds value in index register to that value (10+3=13)
- therefore go to memory address 13 to access data to add.
25
Benefits of Mnemonics
- Simplified --> Easier for a developer to remember compared to binary instructions.
26
explain why LMC instructions BRA / BRP would cause contents of PC to change
- BRA and BRP are branch instructions, equivalent to IF, FOR, WHILE in high level language.
- they change flow of program so next instruction not always executed
27
what is the purpose of the Little Man Computer
- it's a simulator of the Von Neumann architecture and uses the idea of a little man running around between ACC and main memory with the pieces of data required to perform operations such as calculations etc
28
how many memory allocations does it have
100 ( they are numbered 0 to 99)
29
how can you ensure an instruction isn't overwritten when program writes to main memory (where program is loaded)?
- use named locations (using DAT). Or, use high value locations in case you need to add more instructions as you test and debug code.
30
What is an Opcode?
- Part of an instruction that specifies which operation the processor should perform. i.e what to do with data
31
What is Operand?
- contains a value/set of values, relevant to the opcode. it can be an actual piece of data, or a reference to memory location of the data for the opcode to act on. (what to do it to
32
What does operand store if opcode is a STORE instruction
- e.g when the opcode is a 'store' instruction, the operand contains the memory location where the data should be stored.
33
Components in a CPU:
- CU
-Clock
-Buses
-ALU
-Registers
-Cache
34
What is CPU
- internal hardware component of computer, responsible for executing the instructions of programs.
- The processor is made up of several important components, each of which have a specific role.
35
what does the cpu contain that creates logic circuits to process data, do instructions and control computer components
- transistors
36
What is Control Unit
-Coordinates activities of a CPU, directing flow of data in, within + out of cpu i.e organise sequence of micro operations needed to be performed to execute. (manages fde cycle)
-responsible for sending signals to direct flow of data between cpu + other devices and control signals on control bus to enable data to be read (loaded) from and written (stored) to the main memory
-accepts, decodes instruction cpu will execute to determine what needs to be done + stores resulting data to memory/registers
-directing operations of all other components of processor
-determine operation ALU will carry out at each instance
37
what is meant by decoding?
- Decoding means that opcode and operand of an instruction are analysed to determine what needs to be done to execute
38
what does CU use extensively?
- clock and status registers
39
What is the ALU?
- performs arithmetic, logical and bitwise shift operations.
40
what is ALU connected to and why
- set of general-purpose registers used to keep results of the intermediate calculations that are produced as part of a larger one
41
What is a clock?
-emits signal (pulse) that continuously oscillates between a low (0) and a high (1) state --> synchronise operations of the processor components.
42
what is clock period?
- time taken between two sequential rising edges (0 to 1) and it corresponds to 1 clock cycle
43
what is clock speed?
- number of clock cycles that can be completed in one second, measured in Hz.
44
what is clock speed the inverse of
- clock period, i.e. clock frequency=1/clock period.
45
What are registers?
- locations of computer memory within the processor that provide extremely fast access.
46
What are dedicated/special-purpose registers?
- processor-based registers used for specific purpose.
47
why are the registers used in FDE cycle special purpose registers
- as each one of them has specific role to play in each phase of FDE cycle.
48
What is the function of the program counter?
- Holds address of next instruction to be fetched/executed by cpu.
49
What is the function of the current instruction register?
- Holds instruction that is currently being executed by processor.
50
why do we need CIR and not just MDR
- since it stores the instruction to be decoded so that it is not overwritten by additional data fetched to the MDR
51
what does current instruction register contain
- opcode and operand(s) of current instruction
52
What is the function of the memory address register?
- Temporarily holds the memory address from which data or an instruction is to be accessed/fetched or to which data is to be written to.
53
what bus is used to send these addresses to memory
- address bus
54
What is the function of the memory data/buffer register?
- Temporarily stores the data/instructions that has been read from or written to main memory.
-Stores the data from memory location specified by MAR
55
what does memory data/buffer register act like and why
- a buffer between the CPU and the memory so that they can act independently of each other.
56
All data to and from memory must travel down a.) what bus and b.) pass through what register
- data bus
- MDR
57
What is the accumulator?
- stores result of any calculation processed by ALU.
- holds all input/output
- I/O in processor used as a buffer/gateway
58
EXTRA INFO ABOUT ACCUMALATOR
- The processor accesses other general-purpose registers where temporary values are stored while calculations are completed. Any result resides in the accumulator. (general purpose register)
59
What is an interrupt register and what does it do?
- it is checked by cpu to see if an interrupt is awaiting processing. If it is, software process Interrupt Service Routine is invoked and handles interrupt request by interrupting current active process
60
what is a status register?
- contains info about state of processor as individual bits are implicitly / explicitly read and/or written by machine code instructions executing on processor (these bits can be thought of as flags that can be checked)
- Used to store info about the result of the last instruction that the ALU executed. Each bit within the status register acts as a flag to indicate if an error or exception has occurred within the process, or to enable or disable interrupts to be raised:
An error or exception is when the result of a calculation requires further action. For example, it signifies if the result of a calculation is negative or zero, or if a calculation produced an overflow or/and a carry.
An interrupt is an event outside of the program process that requires the attention of the processor. For example, indicating a hardware malfunction.
61
What is a bus?
- set of parallel wires that connect two or more components of a computer.
62
how many lines does bus usually consist of
- 8, 16, 32 or 64 lines.
63
What are the main buses that connect the CPU to the memory and the direction of data flow along these buses?
- address bus (CPU --> memory only)
- data bus (Both directions)
- control bus (Both directions)
64
what is a system bus?
- set of parallel connections that allow 2 or more internal components to be connected and communicate with each other and exchange data.
65
what are external buses?
And name the 2 types of connections that can occur
- used to connect the peripherals to the processor.
- serial or parallel connections
66
What is the function of the address bus?
- carries address of a specific memory location that cpu wants to access (read data from or write data to)
67
what is the address bus average width
- 32 bits
68
What is the function of the data bus?
- Carries data/instructions from RAM to the CPU to be processed and carries processed data from the CPU to the memory
69
what does width of data bus refer to
- number of parallel lines which determines number of bits that can be transferred in 1 operation
70
what does width of address bus refer to
- number of parallel lines which determines number of bits that can be used to form an address of a memory location
- there are 2^n numbers that can be used to address memory locations
71
What is the function of the control bus?
- transmits command and control signals from CU that control and coordinate all activities (timings, status information + bus requests) from processor to other components.
72
give 7 examples of control signals
- memory read
- memory write
- interrupt request
- clock signals
- bus request
- bus grant
- bus busy
73
what does memory read signal do
- Places data from specific memory location (whose address is on the address bus) onto the data bus
74
what does memory write signal do
- Stores data from the data bus onto a specific memory location (whose address is on the address bus)
75
what does bus request do
- Signifies that a component needs to access a bus
76
what does bus grant do
- Signifies a component is informed it can use the bus it requested access to
77
what does bus busy do
- Signifies a bus is not available for use (used by another component)
78
what does interrupt request do
- Signifies an error/exception has occurred that requires attention of CPU
79
what process happens when the processor needs to read a memory location
- read request sent via control bus, along with address of memory location via address bus. These operations happen at the same time (i.e. in the same clock cycle).
- Depending on how long it takes to access memory, CPU then receives contents of that memory location via data bus, after a number of clock cycles.
80
what process happens when the processor needs to write to a memory location
- it sends a write request via control bus, along with address of that memory location via address bus and the data that needs to be stored/written via the data bus.
81
Before the fetch-decode-execute cycle can take place, a program’s instructions need to be ‘ready’ to be carried out. What does this mean?
- program instructions have to be translated into machine code
- program instructions are loaded from secondary storage into RAM
82
what happens at the end of each cycle for each instruction
- the processor checks the status register to see if an error, exception, or interrupt needs to be handled
83
explain fetch stage of FDE cycle
- PC checked as it holds address of next instruction to be executed.
-Address of next instruction copied by PC and placed in MAR.
- Address is transferred along address bus to RAM where it waits to receive signal from control bus.
- CU sends process signal like memory read etc. along control bus to RAM.
- Main memory knows what needs to happen so contents stored in the desired memory location is sent along data bus to MDR.
- Simultaneously, PC increments to next instruction to be processed so that address it contains points to next instruction to be executed.
- Data received by MDR was just fetched from RAM now copied into CIR. INSTRUCTION NOW FETCHED!!
84
describe sequence of processes performed by PC
- stores address of next instruction to be executed
- value copied to MAR
-After sending, PC is incremented or changed to address held in CIR if operation = Jump
85
why does this final stage of fetch stage happen:
Data received by MDR was just fetched from RAM now copied into CIR.
- so current instruction kept safe so MDR can be used during execute stage to store additional data needed
86
explain decode stage of FDE cycle
- Instruction held in CIR now decoded by control unit.
- Instruction made of 2 parts: opcode (what to do) and operand (what to do it to) which could contain data or address where data is found
87
explain execute stage of FDE cycle
- CIR sends address to MAR Then MAR sends address to main memory down address bus.
-CU sends control signal as to what needs to happen to the data along control bus to main memory.
- Content stored in memory at designated address is sent along data bus back to cpu, to MDR.
- Contents of MDR now copied to accumulator. Instruction completed!!
(decoded instruction is executed e.g ALU perform calc with result being stored in ACC, locate data in RAM etc. Processed data sent to RAM through data bus
88
what factors affect the performance of the cpu
- clock speed
- cache
- number of cores
- use of pipelining
89
how does clock speed affect performance of cpu.
state what it is, unit of measure, what each tick of crystal represents and how this links to increasing performance
- Clock speed (frequency clock ticks) vibrating crystal/electronic oscillator that maintains constant speed by producing a signal to sync operation of processor.
-Measured in Hz.
-Each tick of crystal = one step in FDE cycle. Faster clock speed = more instructions executed per sec. So computer processes data faster as more FDE cycles occur per sec.
90
what is cache? describe the levels of cache
- volatile fast storage which stores frequently used data and instructions.
- Different levels of cache: L1 = quickest but lowest capacity, L2 and L3 = slowest but has more capacity
91
how does cache size affect performance of cpu.
- data transferred faster --> faster processing --> faster fetching data --> more cache improves performance as it makes it faster for cpu to access frequently used data from cache rather than CPU fetching data from RAM (RAM accessed less frequently)
92
how does number of cores affect performance of cpu.
state what it is and how it CAN increase performance
- increasing number of cores increases complexity of CU
- core =copy of cpu which can fetch and execute instructions at same time --> can make computer faster but they have to communicate with each other to take turns to access RAM.
93
what is the advantage to performance using an increased number of cores
- parallel processing takes place --> each core can execute a separate instruction simultaneously enabling multitasking as they process faster --> more processes completed per second. Computer performs more efficiently.
94
what is the disadvantage to performance using an increased number of cores
- efficiency of multicore processor depends on nature of task as some processes can't be split between 2 cores so doesn’t increase performance (bottleneck can be created).
-So although doubling cores theoretically doubles speed, in reality computer will run slightly slower.
95
What is pipelining?
When can pipelining be applied to a task?
And what process can this be linked to?
– technique of fetching an instruction whilst prior is being decoded and one before being executed. It used to improve processor performance
- task needs to be able to be broken down into subtasks that can be handled independently.
- FDE cycle (number of distinct stages that are repeated for every instruction).
96
how does pipelining improve performance in terms of FDE cycle
- avoids overwriting data (when one instruction is being executed, another can be decoded, and a third can be fetched).
-This cycle avoids keeping internal components idle so we make efficient use of various registers, cpu + cache and means instructions are executed at a faster rate, which in turn improves processor performance.
97
processor pipelining is divided into what 2 pipelines. Also describe these 2 pipelines
- instruction pipeline (consists of various stages instruction must go through)
- arithmetic pipeline (consists of parts of arithmetic operation that can be broken down and overlapped as they are carried out)
98
what type of programs wouldn't benefit from pipelining and why
- Program with branching instructions as pipe has to be flushed when branching onto different instructions.
99
how does adding more/faster RAM improve computer performance
- more programs can be open simultaneously without need to use slower virtual memory
100
how does replacing CPU for faster one improve computers performance
- may have faster clock speed so execute more instructions per sec.
- may have multiple cores = parallel processing
- it may have more cache so slower RAM accessed less frequently
101
how does updating or installing lighter OS improve computer performance
- OS updates released frequently + some improve performance
- lighter weight OS uses fewer system resources allowing system to devote more time to run user applications
102
how does adding a graphics card improve computer performance
- speeds up rendering of 3D graphics as GPU has specialist instructions + can apply the same instruction to multiple pieces of data simultaneously
103
how does defragmenting a hard disk improve computer performance
- less time spent finding parts of files + stores parts of file contiguously
(fragmented HDD runs slowly as more time spent finding parts of a file)
104
how does checking for malware improve computer performance
- malware slows down computer, remove it improves performance
105
how does upgrading to faster secondary storage improve computer performance
- slower secondary storage = longer it takes to load programs/files/data
- SSD/flash memory can improve this
106
what does von neumann architecture consist of
- shared memory space and buses for instruction and data which are stored in same format too
- single CU follows linear FDE cycle
- 1 instruction at a time (each cycle must be finished before next one begins)
- registers used as fast access to instructions + data
107
what does harvard architecture consist of
- instructions and data stored in separate memory units
- each have their own bus
- reading + writing data can be done at same time as fetching an instruction
- used by RISC processors
108
what are contemporary architectures. gives examples
- more modern high performance CPU chips which incorporate aspects of both Von Neumann and Harvard machine architectures
- MIMD, distributed computing
109
what does SIMD stand for, what is it a form of and what is it mainly used by
- Single Instruction Multiple Data
- array processing is where processor carries out single instruction on multiple data items at same time (carries out same operation on multiple data items at once)
- often used by graphic processors
110
SIMD computers use array processing. When can array processing not occur
- when the data relies on another item of data to be processed before it can be processed
111
what is distributed computing
- multiple computers on a shared network each take on part of a bigger problem (can be done on grand scale)
112
what does MIMD stand for
what is it
what type of processing does it use
- Multiple Instruction Multiple Data
- where multiple instructions carried out on multiple data items across several cores (parallel processing)
113
To which registers could the current instruction register pass an operand to depending on the instruction and mode of addressing?
- ACC, MAR, PC
- CIR stores address of instruction currently being decoded + executed. The operand part of the instruction is passed to PC if it is a branch instruction, MAR if command requires data from memory, or possibly the accumulator if operand is the data to be used by the instruction.
114
where are harvard architecture processors found
- embedded systems, digital signal processing, mobile communication, speech and image processing systems
115
compare the sizes of programs for von neumann and harvard architectures
- optimised programs = von neumann
- large programs = harvard
116
compare the speed and cost of von neumann and harvard architectures
- von neumann is slower but cheaper
- harvard is faster but more expensive
117
true or false: modern CPUS incorporate aspects of both von neumann and harvard architecture. And what is this architecture called?
- true
- contemporary architectures
118
in von neumann architecture, do data and instructions use same word size or not
- they use same word size
119
what causes bottlenecks in von neumann architecture
- caused by single bus
- the CPU is left idle while it waits for data to be sent
120
what partially mitigates the impact of von neumann bottlenecks.
- use of cache (prefetching used whereby instructions and data expected to be used first are fetched into cache in advance so they're immediately there when needed)
