1.1.1 Structure and Function of the Processor

Question 1

What is the purpose of the ALU and the CU?

Answer 1

• The Arithmetic and Logic unit completes mathematical and logical operations on data.
• The control unit uses signals to direct the operations of the CPU. It manages data flow, decodes instructions and coordinates the processors.

Question 2

What is a register, and what do the main 5 each do?

Answer 2

• They are small high speed memory cells, temporarily holding data.
• The PC holds the address of the next instruction to be executed.
• The ACC stores calculation results.
• The MAR holds the address of a location to be read/written to.
• The MDR holds read/to be written data.
• The CIR holds the current instruction (operand and opcode).

Question 3

What is a bus, and what do they each do?

Answer 3

• They are sets of parallel wires connecting processor components. The number of wires affects the number of bits that can be simultaneously transmit.
• The Data bus is a bidirectional bus used for transmitting data and instructions.
• The Address bus transmits memory addresses.
• The Control bus is a bidirectional bus used to send control signals between internal and external components. (IE clock, write, requests, interrupts).

Question 4

How do assembly language instructions work?

Answer 4

• Mnemonics represent instructions as simplified machine code.
• An instruction contains an operand (the data or address of data) and opcode (the type of instruction to be executed on the data).

Question 5

What is the purpose of pipelining?

Answer 5

• Completing the FDE cycle of 3 instructions simultaneously by holding data in a CPU-close buffer.
• Reduces CPU idleness by fetching, decoding and executing simultaneously.

Question 6

What are the steps of the FDE cycle?

Answer 6

Fetch:
- PC address copied to MAR, instruction at address copied to MDR by data bus.
- PC incremented, MDR instruction copied to CIR.
Decode:
- CIR contents split into operand and opcode.
Execute:
- Decoded instruction is now executed using whichever registers are needed.

Question 7

What factors affect the performance of the CPU?

Answer 7

• A higher clock speed means more FDE cycles can be complete in a second, timed by a clock generating alternating 0/1 signals.
• A greater number of cores (independent processors performing FDE cycles) boosts performance of optimised applications.
• The type of cache memory and its transfer rate. Lower levels of cache hold less but transfer much faster, holding frequently used data/instructions.

Question 8

What are the differences between Von Neumann and Harvard Architecture?

Answer 8

• Von Neumann includes a shared memory containing data and instructions with one bus. Allows for cheaper, size optimised programs and a simpler CU.
• Harvard architecture has physically separate instruction and data memories and two buses. Allows for different sizes and properties of memories, and faster execution.
• Contemporary processors are often using combined architecture types.