1.1.1 Structure and function of the processor Flashcards
alu
arithmetic logic unit => performs any arithmetic/logic operations
cu
control unit =>
* decodes instructions
* sends control signals to coordinate how date moves through the processor
pc
program counter =>
* a register that holds the address of the next instruction to be executed
* can be changed by branch instructions
* incremented by 1 every FDE cycle
acc
accumulator =>
* acts as a buffer
* temp stores result of calculations from the alu
mar
memory address register =>
* holds the address from the pc
* and data/instructions to be fetched/written to
mdr
memory data register =>
* temporarily stores data/instructions that have been read/written to
* acts as a buffer
cir
current instruction register =>
* holds the address of the current instruction being executed
* divided into operand/opcode
fetch stage
- contents of pc => mar
- pc incremented by 1
- read signal sent onto control bus
- instruction ram => mdr via data bus
- data copied mdr => cir
decode stage
- cu decodes
- split into operand/opcode
execute stage
opcode carried out on the operand
4 cases:
* getting: ram=>acc
* writing: acc=>ram
* alu related
* pc changed:
clock speed
- num of clock cycles per second increased
- instructions executed per secons increased
- less time to run
num cores
- each core can process a different instruction at the same time w/ its own FDE cycle
- software may not be able to take advantage of both processors
cache
- more space for data/inst
- ram needs to be accessed less frequently
- accessing is quicker than ram
pipelining
- one instrucution fetched as the other one is being decoded and another is executed
- concurrent processing of multiple instructions
- inc. speed of execution
- reduces latency
- all parts of the processor used at the same time
von neumann
- data/inst => stored in the same memory and in the same format => space efficient
- so simple circuitry => cheaper
- has FDE cycle
- has ALU
