1.1.1 Structure and function of the processor Flashcards
To Win (27 cards)
Control Unit
part of the processor that coordinates the activity of all other components
Control Signals
signals sent along the control bus between the control unit and other components
Control Signal: Memory Read
data from the addressed location in RAM to be placed on the data bus
Control Signal: Memory Write
data on the data bus to be written into the addressed location in RAM
Control Signal: Bus Request
indicates that a device is requesting
use of the data bus
Control Signal: Bus grant
indicates that the CPU has granted access to the data bus
Control Signal: Clock
Used to synchronise operations
Bus
Series of connectors that transfer signals
System Bus
Three separate buses carrying control signals, addresses and data
Arithmetic Logic Unit (ALU)
Performs logical, arithmetic and shift operations
Accumulator (ACC)
register of super-fast memory that stores results from ALU
Program Counter (PC)
holds the memory address of next instruction
Current Instruction Register (CIR)
holds the current instruction and split into opcode and operand
CIR: Opcode
specifies the operation to be carried out
CIR: Operand
contains address of data to be copied to MAR
OR
contains actual data to be operated on to be passed to MDR
Memory Address Register (MAR)
holds the address of memory location
Memory Data Register (MDR)
holds the data moving between the processor and memory
Fetch Stage: Component order
PC -> MAR
MAR -> MDR (PC + 1)
MDR -> CIR
Fetch Stage (PC -> MAR)
Address of next instruction is copied from PC to MAR
Fetch Stage (MAR -> MDR {PC + 1})
Instruction at address in MAR is copied to MDR, simultaneously the PC is incremented by 1
Fetch Stage (MDR -> CIR)
Content in MDR is copied to CIR
Decode Stage (CIR)
The instruction in the CIR is decoded
Decode Stage (CIR)
Splits into Opcode and Operand to determine type of instruction
Opcode
What operation needs to be carried out
